Circuit arrangement for reading out and regenerating items of in

Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing

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365222, G11C 700

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active

042901200

ABSTRACT:
A circuit arrangement is disclosed for reading out and regenerating items of information stored in one-transistor storage elements. For read-out, storage elements addressed by the activation of a word line transfer an existing information charge into assigned bit lines, and wherein the bit lines influence inputs of assigned read-out/regenerating amplifiers. The storage density of semiconductor stores is increased by providing a circuit arrangement in which the disproportion in terms of area between technologically realizable storage matrices and the required amplifiers which is a by-product of the miniaturization of stores of the above mentioned type does not occur. A group of m bit lines are in each case combined to form groups and are consecutively connected via a multiplexer to a common read-out/regenerating amplifier.

REFERENCES:
patent: 4160275 (1979-07-01), Lee et al.
Heller et al., "High-Sensitivity Charge-Transfer Sense Amplifier", 1975 IEEE International Solid-State Cir. Conf., 2/13/75, pp. 112-113.
Hoffmann, "Continuously Charge-Coupled Random-Access Memory (CCC RAM)", 1976 IEEE International Solid-State Cir. Conf., 2/19/76, pp. 130-131.
Tasch et al., "The Charge-Coupled RAM Cell Concept," IEEE Trans. on Electron Devices, vol. Ed. 23, No. 2, Feb. 1976, pp. 126-131.
Karte, "Cache Memory," Elektronik, 1974, p. 12.

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