Circuit arrangement for driving an MOS field-effect transistor a

Electronic digital logic circuitry – Interface – Current driving

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326 86, 326 17, 327432, H03K 190175, H03K 301

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active

058412972

ABSTRACT:
A circuit arrangement 10 for driving an MOS field-effect transistor QO allocated to the supply circuit KO of an electrical load R.sub.L contains a charging circuit K1 and a discharging circuit K2, which can be alternatively connected to the MOS field-effect transistor QO. A sensing circuit K3 supplies the measuring signal S.sub.M typical of gate-source voltage U.sub.GS of the MOS field-effect transistor QO, via which the internal resistance of the charging or discharging circuit K1, K2 and/or a current I.sub.a impressed upon these circuits K1, K2, in the sense of a positive feedback, is controlled, in such a way that the resulting time constant, according to which the input capacitance of the MOS field-effect, transistor QO is charged or discharged, becomes smaller during the transition of the MOS field-effect transistor QO from the off state to the conductive state and larger during the transition from the conductive to the off-state.

REFERENCES:
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patent: 5120999 (1992-06-01), Schreck et al.
patent: 5463331 (1995-10-01), Kuo
patent: 5539336 (1996-07-01), Nguyen et al.
patent: 5548240 (1996-08-01), Bayer
patent: 5576641 (1996-11-01), Yoneya et al.
patent: 5614847 (1997-03-01), Kawabara et al.
patent: 5644258 (1997-07-01), Wu

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