Circuit arrangement comprising a matrix-shaped memory arrangemen

Details Circuit arrangement comprising a matrix-shaped memory arrangemen Circuit arrangement comprising a matrix-shaped memory arrangemen

1986-02-12

1988-04-26

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Signals

365189, G11C 700

Patent

active

047409240

ABSTRACT:
A circuit arrangement for providing a variably adjustable time delay of digital signals comprises a matrix-shaped memory arrangement having storage elements with overlapping write/read cycles. A clock-controlled, continuously steppable row selector normally cyclically circulates, but can be reset at any time. The row selector comprises two mutually phase offset signal outputs per selection step which respectively drive a write word line and a read word line of a word of the matrix. Two separate bit lines, a write bit line and a read bit line, are provided per column and are respectively interconnected to all memory cells of a column. The data input for the data signal to be delayed is connectible to all write bit lines via gates individually assigned to the columns, whereby only one of m gates is activated at a time by the column selector.

REFERENCES:
patent: 3893088 (1975-07-01), Bell

Affiliated with

Also associated with

Rating

Circuit arrangement comprising a matrix-shaped memory arrangemen does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit arrangement comprising a matrix-shaped memory arrangemen, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit arrangement comprising a matrix-shaped memory arrangemen will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-824242