Circuit arrangement and method for secure data processing

Details Circuit arrangement and method for secure data processing Circuit arrangement and method for secure data processing

2006-02-15

2009-08-11

Baker, Stephen M (Department: 2112)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S052000, C714S807000, C714S811000

Reexamination Certificate

active

07574631

ABSTRACT:
Circuit arrangement for secure data processing for program data with a protected data record. An internal memory provides a protected data record having instruction words and a first check word associated with the instruction words. An arithmetic and logic unit has an input coupled to the internal memory and outputs the first check word from the applied protected data record. A checking apparatus has an input coupled between the internal memory and the arithmetic and logic unit, and allocates a second check word to the instruction words in the protected data record. A comparison apparatus has respective inputs coupled to the checking apparatus and the arithmetic and logic unit, and compares the first check word with the second check word, and outputs an alarm signal when the first check word does not match the second check word.

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