Circuit arrangement and method for recognizing manipulation...

Details Circuit arrangement and method for recognizing manipulation... Circuit arrangement and method for recognizing manipulation...

2011-03-29

2011-03-29

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S185040

Reexamination Certificate

active

07916517

ABSTRACT:
A circuit arrangement having complementary data lines of a dual rail data bus, wherein in a regular operating phase the complementary data lines carry complementary signals, and in a precharge phase the complementary data lines assume an identical logic state or the same electrical potential. The circuit arrangement also has a device for detecting manipulation attempts, the device having a detector circuit, which outputs an alarm signal upon the occurrence of an identical logic state on both data lines in the regular operating phase.

REFERENCES:
patent: 4328583 (1982-05-01), Stodola
patent: 4342112 (1982-07-01), Stodola
patent: 5483542 (1996-01-01), Nguyen
patent: 6225826 (2001-05-01), Krishnamurthy et al.
patent: 6253350 (2001-06-01), Durham et al.
patent: 6947342 (2005-09-01), Ishida et al.

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