Circuit arrangement and method for producing a dual-rail signal

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor

Reexamination Certificate

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C326S093000, C326S097000

Reexamination Certificate

active

10965663

ABSTRACT:
Circuit arrangement for producing a dual-rail output signal having a signal processing apparatus with two switches, which are driven as a function of an input signal, a first output connected via one of the switches to a signal processing apparatus foot point, which is at a first potential, and a second output connected via the other switch to the foot point. The signal processing apparatus is connected via a switching apparatus to outputs of the circuit arrangement in order to output a dual-rail output signal. The outputs of the switching apparatus are each connected to one or to both inputs of the switching apparatus as a function of a control signal. A potential monitoring apparatus defines the potentials at the outputs of the circuit arrangement when these outputs are not connected via the switching apparatus and the signal processing apparatus to the foot point of the signal processing apparatus.

REFERENCES:
patent: 4570084 (1986-02-01), Griffin et al.
patent: 5550487 (1996-08-01), Lyon
patent: 5815005 (1998-09-01), Bosshart
patent: 5859548 (1999-01-01), Kong
patent: 5966382 (1999-10-01), Fawal et al.
patent: 6069497 (2000-05-01), Blomgren et al.
patent: 6331791 (2001-12-01), Huang
patent: 6374393 (2002-04-01), Hirairi
patent: 6459316 (2002-10-01), Vangal et al.
patent: 6466057 (2002-10-01), Naffziger
patent: 6570409 (2003-05-01), Ananthanarayanan et al.
patent: 6686776 (2004-02-01), Sakata et al.
patent: 6828909 (2004-12-01), Script et al.
patent: 0 334 050 (1989-02-01), None
patent: 0 440 514 (1991-08-01), None
patent: 1 126 611 (2001-08-01), None
patent: 1 168 625 (2002-01-01), None
patent: 60-114029 (1985-06-01), None
patent: 61-264820 (1986-11-01), None
patent: 61-264820 (1986-11-01), None
patent: 05-175827 (1993-07-01), None
patent: 60-061842 (1994-03-01), None
patent: 10117140 (1998-05-01), None
patent: 1008909 (1983-03-01), None
patent: WO 01/63767 (2001-08-01), None
Hong-Yi Huang et al.; “New CMOS Differential Logic Circuits for True-Single-Phase Pipelined Systems”; Circuits and Systems, 1994, pp. 15-18, month n/a.
Chun-Keung Lo et al; “Design of Low Power Differential Logic Using Adiabatic Switching Technique”; Circuits and Systems, 1998, pp. 33-36, March.
Kazuo Yano et al; “A 3.8-ns CMOS 16×16-b Multiplier Using Complementary Pass-Transistor Logic”; IEEE Journal of Solid-State Circuits, Apr. 1990, vol. 25, No. 2, New York, US, pp. 388-395.
Fang-shi Lai et al.; “Design and Implementation of Differential Cascode Voltage Switch with Pass-Gate (DCVSPG) Logic for High-Performance Digital Systems”; IEEE Journal of Solid-State Circuits, vol. 32, No. 4, Apr. 1997, New York, US, pp. 563-573.
“Asymmetric Transition Dual-Rail Signalling”; IBM Technical Disclosure Bulletin, vol. 37, No. 1, New York, US, pp. 69-84, Jan. 1994.
Russian Notice of Allowance dated Apr. 20, 2006.

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