Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1996-12-10
2000-05-02
Tokar, Michael
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326 95, 326 98, H03K 19096
Patent
active
060577118
ABSTRACT:
A circuit arrangement, system, and method provide asynchronous control of a state logic circuit to facilitate testing of the state logic circuit. The state logic circuit includes stages selectively enabled by a clock signal that generate an output signal as a function of a history of a data signal. Upon application of a control signal, the alternate enabling circuit enables at least one of the stages regardless of the state of the clock signal, such that the output signal does not depend on the history of the data signal.
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Le Don Phu
Tokar Michael
VLSI Technology Inc.
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