Circuit area minimization using scaling

Details Circuit area minimization using scaling Circuit area minimization using scaling

2006-10-03

2006-10-03

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07117456

ABSTRACT:
A method, system and program product that implements area minimization of a circuit design while respecting the explicit and implicit design constraints, in the form of ground rules and user intent. A longest path algorithm is used to generate a scaling factor. The scaling factor is used to reduce the size of the circuit design to the minimum legal size. The scaling may be followed by application of minpert analysis to correct any errors introduced by the scaling. The resulting design is shrunk (or expanded) with all elements shrinking (or growing) together by the same factor, and with the relative relationships of elements maintained. In addition, the invention is operational in the presence of a positive cycle, can be run with scaling that freezes the sizes of any structure or ground rule, and can be applied to technology migration.

REFERENCES:
patent: 5231590 (1993-07-01), Kumar et al.
patent: 5406497 (1995-04-01), Altheimer et al.
patent: 5416722 (1995-05-01), Edwards
patent: 5477467 (1995-12-01), Rugg
patent: 5598344 (1997-01-01), Dangelo et al.
patent: 5619419 (1997-04-01), D'Haeseleer et al.
patent: 5625568 (1997-04-01), Edwards et al.
patent: 5636132 (1997-06-01), Kamdar
patent: 5663892 (1997-09-01), Hayashi et al.
patent: 5689433 (1997-11-01), Edwards
patent: 5889681 (1999-03-01), Suda
patent: 5936868 (1999-08-01), Hall
patent: 5974244 (1999-10-01), Hayashi et al.
patent: 6044208 (2000-03-01), Papadopoulou et al.
patent: 6099584 (2000-08-01), Arnold et al.
patent: 6189132 (2001-02-01), Heng et al.
patent: 6202193 (2001-03-01), Emura et al.
patent: 6216252 (2001-04-01), Dangelo et al.
patent: 6295633 (2001-09-01), Murakawa
patent: 6378114 (2002-04-01), Shenoy et al.
patent: 6412097 (2002-06-01), Kikuchi et al.
patent: 6412100 (2002-06-01), Sasagawa et al.
patent: 6434721 (2002-08-01), Chiluvuri et al.
patent: 6507931 (2003-01-01), Kotani et al.
patent: 6526555 (2003-02-01), Teig et al.
patent: 6576147 (2003-06-01), Mukai
patent: 6587992 (2003-07-01), Marple
patent: 6874133 (2005-03-01), Gopalakrishnan et al.
patent: 2005/0060672 (2005-03-01), Poechmueller
patent: 2001339312 (2001-12-01), None
Heng, F, et al., “A VLSI Artwork Legalization Technique Based on a New Criterion of Minimum Layout Perturbation”, Proceedings of the 1997 International Symposium on Physical Design, pp. 116-121.
Chen, Z, et al. “A Fast Minimum Layout Perturbation Algorithm for Electromigration Reliability Enhancements”, 1998 Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems, Nov. 2-4, 1998, pp. 56-63.
“Flexible Image for Physical Layout of Circuits,” A. R. Bruss et al., IBM Technical Disclosure Bulletin, vol. 27, No. 11, Apr. 1985, pp. 6687-6691.
“An Algorithm to Detect Positive Cycles in a Constraint Graph for Layout Compaction,” K. Ishima et al., IEEE, CH2868-8/90/000-2853, 1990, pp. 2853-2856.
“Process Independent Constriant Graph Compaction,” D. Boyer, 29th ACM/IEEE Design Automation Conference, Paper 21.4, pp. 318-322.
“An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints,” Y. Z. Liao et al., 20th Design Automation Conference, Paper 9.1, IEEE, 1983, pp. 107-112.
“Graph-Optimization Techniques for IC Layout and Compaction,” G. Kedem et al., 20th Design Automation Conference, Paper 9.2, IEEE, 1983, pp. 113-120.
“Symbolic Layout Compaction Review,” D. Boyer, 25th ACM/IEEE Design Automation Conference, Paper 26.1, 1988, pp. 383-389.
“A Subjective Review of Compaction,” Y. Cho, 22nd Design Automation Conference, Paper 25.1, IEEE, 1985, pp. 396-404.
“An Introduction to VLSI Physical Design,” M. Sarrafzadeh et al., Chapter 7, “Compaction,” Section 7.1.2, “Graph-based Techniques,” McGraw-Hill (1996), pp. 276-279.
“Algorithms for VLSI Physical Design Automation,” 3rd Edition, N. Sherwani, Chapter 12, “Compaction,” Section 12.3.1, “Constraint-Graph based Compaction,” Kluwer Academic Publishers (1999), pp. 453-463.

Affiliated with

Also associated with

Rating

Circuit area minimization using scaling does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit area minimization using scaling, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit area minimization using scaling will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3641711