Circuit architecture for effective compensating the time...

Details Circuit architecture for effective compensating the time... Circuit architecture for effective compensating the time...

2011-04-05

2011-04-05

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S029000, C327S155000

Reexamination Certificate

active

07919989

ABSTRACT:
A circuit architecture for effective compensating the time skew of circuit is disclosed. The circuit architecture comprises a required compensation circuit, two duplicated circuits, and a time skew detection and compensation circuit, wherein these duplicated circuits are the duplicates of the required compensation circuit. A differential of logic 0 and logic 1 signals are simultaneously inputted into two duplicated circuits to output a first detection signal and a second detection signal, then the time skew detection and compensation circuit detects the time skew between a first detection signal and a second detection signal so as to generate a compensation signal to the required compensation circuit. Accordingly, the time skew existed in the required compensation circuit can be reduced or eliminated.

REFERENCES:
patent: 6340905 (2002-01-01), Schultz
patent: 7616022 (2009-11-01), Hur et al.
patent: 2006/0244505 (2006-11-01), Fung et al.
patent: 2009/0273381 (2009-11-01), Kim et al.
patent: 2010/0052745 (2010-03-01), Chung et al.

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