Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-07-30
2001-10-30
Beausoleil, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S031000
Reexamination Certificate
active
06311292
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to debugging operations for a microprocessor.
BACKGROUND
Designers have attempted to keep microprocessor debugging techniques apace with the faster microprocessors. As a result, these debugging methods have had to undergo recent change. For example, functions that were once a part of separate emulator tools have been integrated into the processor itself. This has alleviated the often difficult task of emulating the various processor types in order to perform simple debugging operations. Most microprocessors are caused to enter a debugging mode through software instructions which are provided to the microprocessor from external memory which is coupled to the microprocessor by a system bus. These software instructions are received by the microprocessor and decoded by a decoder in the microprocessor, and the decoded instruction causes the microprocessor to enter the debugging mode and to perform debugging operations in the manner specified further by the software instructions. This type of microprocessor thus typically requires no extra input or output pins to accommodate these debugging operations because the input and output to/from the microprocessor is through the microprocessor's system bus interface. Thus, this type of microprocessor is generally preferred and may be referred to as an internal programmable debug method.
Some logic devices, such as complex programmable logic devices, have used a different mechanism for entering and performing debugging mode by using a dedicated test port having its own set of dedicated input/output pins on the logic device. One such example is the Joint Test Action Group (JTAG) IEEE 1149.1 Standard which describes a dedicated test port for a logic device. The method of using an external, dedicated test port to debug a logic device may be referred to as an external debug method.
In order to permit users to test a processor without having to purchase specialized debugging tools, it is desirable to offer a microprocessor that offers the advantages of external, dedicated test access port debugging as well as internal programmable methods. Furthermore, it is beneficial to create a microprocessor with an open architecture, so that a user may select from a broad range of microprocessor debugging standards, be it JTAG or internal programmable method or any other standard.
SUMMARY OF THE INVENTION
Described herein is a microprocessor, a computer architecture and a method that allows dual access to debugging operations. In one embodiment, the present invention provides a method of interrupting normal microprocessor operation and performing a debugging operation on the microprocessor. This debugging operation may be either through an internal programmable method or through an external dedicated test port to the microprocessor, depending on which mode is selected. Furthermore, both the internal or external debugging modes may be interrupted. This may occur, for example, after the debugging operation is complete. In any case, the microprocessor may resume normal operation after the debugging operation is interrupted.
In one example of the present invention, a microprocessor includes a system bus interface and a program decoder which is coupled to the system bus interface. The system bus interface is coupled to a system bus to which external memory is coupled. Debugging operations are stored as debugging instructions in the external memory. When these debugging instructions are retrieved from memory, through the system bus and the system bus interface, they are decoded in the program decoder of the microprocessor and they in turn cause the microprocessor to enter a first debugging mode which is controlled by the debugging instructions. The first debugging mode may be referred to as an internal programmable method. The microprocessor also includes a dedicated test port, such as a JTAG port, which provides signals to and from registers and other logic in test port logic on the IC (integrated circuit) of the microprocessor. The dedicated test port includes input/output pins on the microprocessor which convey the test signals to an external test logic device, such as JTAG test equipment. Testing of the microprocessor using the dedicated test port involves asserting a signal in the test port which causes the microprocessor to enter a second debugging mode which is controlled by the external test logic device. This second debugging mode may be referred to as an external debug method.
In another embodiment, normal microprocessor operation may be interrupted after comparing an established preset value to a present value. As a result, depending on the result of such comparison, normal microprocessor operation may be interrupted for subsequent debugging operations. For example, the preset value may be an instruction stored in a predetermined address register. When the present value is determined, for example, by the microprocessor executing the same instruction that is stored in the predetermined address register, normal microprocessor operation may be interrupted. Alternatively, normal microprocessor operation may be interrupted when the instruction stored in the predetermined register and the instruction executed by the microprocessor are not the same.
In another embodiment, normal microprocessor operation may be interrupted after comparing a preset value, comprising a stored data signal, to a present value, comprising a data signal being read or written. For example, the preset value may be a data value stored in a predetermined address register. When the present value is determined, for example, by the microprocessor reading the data stored in the predetermined address register, normal microprocessor operation may be interrupted. Alternatively, normal microprocessor operation may be interrupted when the data stored in the predetermined address register is being accessed and overwritten.
In another embodiment, the present invention may select either internal debugging operation or external debugging operation, depending on a preset condition. For example, if the preset condition places a debug module in a reset state, the internal debugging operation may be selected. The internal debugging features may be compatible with an N-Wire or N-Trace standard from Hewlett-Packard of Palo Alto, Calif. Also, if the preset condition places the debug module in a non-reset state, the external debugging operation may be selected. Furthermore, the external debugging operation may be accessed by a test port which may be compatible with JTAG IEEE 1149.1 standard.
In yet another embodiment, the present invention provides a microprocessor coupled to a physical system interface that permits debugging external to the microprocessor unit. This external debugging interface may comprise an access port compatible with JTAG IEEE 1149.1 standard. In addition, the present invention includes a programmable logic circuit, internal to said microprocessor, that permits the microprocessor to be debugged by decoding and executing software instructions which are received by the microprocessor from external memory through a system bus interface. The present invention also includes a debug module, coupled between the microprocessor and the physical system interface, which contains logic necessary to select between the external and internal debugging operations. For example, when the debug module is in a reset state it may direct the microprocessor to perform an internal debugging operation.
REFERENCES:
patent: 5497456 (1996-03-01), Alexander
patent: 5983017 (1999-11-01), Kemp
Choquette Jack H.
Smith Donald W.
Beausoleil Robert
Blakely & Sokoloff, Taylor & Zafman
Bonzo Bryce P.
SandCraft, Inc.
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