Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-03-25
2001-07-17
Tse, Young T. (Department: 2634)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C370S516000, C331S014000
Reexamination Certificate
active
06263034
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to digital communications, and more specifically to digital reduction of jitter transfer.
2. Description of the Prior Art
In order to facilitate optimal sampling of input data in a digital communication system or subsystem, such as in a transceiver, demultiplexor or repeater circuit, jitter must generally be tracked and attenuated. Jitter may be defined as a deviation from an ideal timing event and generally arises when a digital signal varies from its ideal position in time. Jitter is typically introduced via a transmitter, transmission media, noise or combination thereof, with the predominate source of jitter being a function of the specific communication link.
There are generally two types of jitter, commonly referred to as random jitter and deterministic jitter, the sum of which yields the total jitter at a specific reference plane in a communication system. Random jitter is the result of the random nature of noise sources within any non-ideal device. Sources of random noise include, but are not limited to, thermal, shot and flicker noise. Random noise sources add, root-mean-square-wise, to generally comprise the entire random jitter contribution of a system or subsystem. The predominant random noise source is a complex function of the system or subsystem implementation and the operational bandwidth.
Deterministic jitter results from systematic sources that by their nature can be “determined”. Examples of deterministic jitter include, but are not limited to, duty cycle distortion, unequal rise and fall times for the devices used in the system's implementation, dispersion due to interconnect media and distortion caused by the different frequencies which propagate through a transmission media at different phase velocities. Since high frequency components of a signal are generally attenuated more than lower frequency components of the same signal, deterministic jitter tends to be prevalent in broad bandwidth systems.
As jitter accumulates in a communication channel, it becomes difficult for a receiver to determine what digital signal was sent by a transmitter, resulting in errored bits. As the amount of jitter increases, the likelihood that the original digital signal cannot be determined correspondingly increases, typically resulting in a loss of information. In order to prevent a catastrophic loss of information, the digital signal must generally be re-timed and re-transmitted before the signal has degraded beyond acceptable levels. Once the signal has been re-timed and the jitter removed or attenuated, the signal can be re-transmitted to a subsequent site or node in a communication system or network.
Continuous monitoring and attenuation of jitter is thus important in maintaining the integrity of a data communication system. However, presently known devices and methods for attenuating jitter have been found to be unsatisfactory. In particular, conventional approaches rely upon re-timing and data recovery circuits for tracking and attenuating random and deterministic jitter. Such approaches tend to be data transmission protocol dependent and complex, resulting in higher power consumption and cost, larger size and lower system reliability. Consequently, jitter and other undesirable variations are often passed onto or transferred to the recovered clock and data.
What is needed therefore is a method and apparatus for tracking and minimizing jitter which is simple, reliable and economical.
SUMMARY OF THE INVENTION
In a first aspect, the present invention provides a jitter reduction circuit for attenuating jitter associated with a signal, including means for generating a first clock and a second clock, phase comparing means for comparing a phase of the first clock with a phase of the signal and adjusting the phase of the first clock in response thereto, means for determining relative phase offset between the first clock and the second clock and selectively changing phase a of the second clock when the phase offset exceeds a tracking range and means for re-timing the signal according to the second clock.
In another aspect, the present invention provides a method for attenuating jitter associated with a signal, including the steps of generating a first clock and a second clock, comparing a phase of the first clock with a phase of the signal and adjusting the phase of the first clock in response thereto, determining relative phase offset between the first clock and the second clock and selectively a changing phase of the second clock when the phase offset exceeds a tracking range and re-timing the signal according to the second clock.
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Kanack Bradley M.
Liu Yi
McDonald James E.
Christie Parker & Hale LLP
Tse Young T.
Vitesse Semiconductor Corporation
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