Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2005-05-10
2005-05-10
Nguyen, VanThu (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189070, C711S102000, C711S154000, C711S163000, C714S710000
Reexamination Certificate
active
06891765
ABSTRACT:
The present invention concerns an apparatus comprising a memory, a logic circuit and a multiplexer. The memory generally comprises a first address space configured as read only and a second address space configured as read and write. The memory returns a first data item in response to a first address within the first address space. The logic circuit may be configured to (i) deassert a command signal in response to the first address not matching any of a plurality of predetermined addresses and (ii) generate a first branch instruction and assert the command signal in response to the first address matching one of the predetermined addresses in response to the matching. The multiplexer may be configured to select the first data item from the memory or the first branch instruction from the logic circuit in response to the command signal.
REFERENCES:
patent: 4610000 (1986-09-01), Lee
patent: 6158018 (2000-12-01), Bernasconi et al.
patent: 6421283 (2002-07-01), Walley et al.
patent: 6438664 (2002-08-01), McGrath et al.
patent: 20030051119 (2003-03-01), Li et al.
patent: 2373888 (2002-10-01), None
Maiorana PC Christopher P.
Nguyen Van-Thu
Via Telecom, Inc.
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