Circuit and methods to improve the operation of SOI devices

Details Circuit and methods to improve the operation of SOI devices Circuit and methods to improve the operation of SOI devices

1998-04-22

2000-12-12

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257349, 257350, 257352, H01L 2701, H01L 2712, H01L 310392

Patent

active

061602922

ABSTRACT:
According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground. This would enable the circuit to retain most of the speed advantages associated with SOI devices while overcoming the loading problem described above. With this preferred embodiment of the present invention, the major delay caused by the bipolar loading effect is minimized while the speed advantage due to providing a lower, variable Vt effect is preserved. The overall body resistance of the individual devices has a minimal effect on the device body potential.

REFERENCES:
patent: H1435 (1995-05-01), Cherne et al.
patent: 3916169 (1975-10-01), Cochran et al.
patent: 3990056 (1976-11-01), Luisi et al.
patent: 4006458 (1977-02-01), Booher
patent: 4169233 (1979-09-01), Haraszti
patent: 4253162 (1981-02-01), Hollingsworth
patent: 4494015 (1985-01-01), Frieling et al.
patent: 4513431 (1985-04-01), Chamberlain et al.
patent: 4700086 (1987-10-01), Ling et al.
patent: 4946799 (1990-08-01), Blake et al.
patent: 5045916 (1991-09-01), Vor et al.
patent: 5120668 (1992-06-01), Hsu et al.
patent: 5145802 (1992-09-01), Tyson et al.
patent: 5234535 (1993-08-01), Beyer et al.
patent: 5258318 (1993-11-01), Buti et al.
patent: 5276338 (1994-01-01), Beyer et al.
patent: 5293052 (1994-03-01), Cherne et al.
patent: 5317181 (1994-05-01), Tyson et al.
patent: 5391510 (1995-02-01), Hsu et al.
patent: 5405795 (1995-04-01), Beyer et al.
patent: 5420055 (1995-05-01), Vu et al.
patent: 5426605 (1995-06-01), Berkel et al.
patent: 5448513 (1995-09-01), Hu et al.
patent: 5466625 (1995-11-01), Hsieh et al.
patent: 5484738 (1996-01-01), Chu et al.
patent: 5489792 (1996-02-01), Hu et al.
patent: 5498882 (1996-03-01), Houston
patent: 5521399 (1996-05-01), Chu et al.
patent: 5521414 (1996-05-01), Palara
patent: 5528062 (1996-06-01), Hsieh et al.
patent: 5567533 (1996-10-01), Hsu et al.
patent: 5573964 (1996-11-01), Hsu et al.
patent: 5599725 (1997-02-01), Dorleans et al.
patent: 5622881 (1997-04-01), Acocella et al.
patent: 5633522 (1997-05-01), Dorleans et al.
patent: 5643813 (1997-07-01), Acocella et al.
patent: 5663578 (1997-09-01), Hsu et al.
patent: 5675164 (1997-10-01), Brunner et al.
patent: 5689127 (1997-11-01), Chu et al.
patent: 5729039 (1998-03-01), Beyer et al.
patent: 5736891 (1998-04-01), Buti et al.
patent: 5753525 (1998-05-01), Hsu et al.
patent: 5759907 (1998-06-01), Assaderaghi et al.
patent: 5977593 (1999-11-01), Hara
patent: 5986867 (1999-11-01), Duvvury et al.
E. Dubois, et al.,Anomalous Voltage Overshoot During Turn-Off of Thin-Film n-Channel SOI MOSFET's, IEEE Electron Device Letters, vol. 14, No. 4, Apr. 1993.
Jacques Gautier, et al. On the Transient Operation of Partially Depleted SOI NMOSFET's, IEEE Electron Device Letters, vol. 16, No. 11, Nov. 1995.
Dongwook Suh, et al. Physical Modeling of Beneficial Dynamic Floating-Body Effects in Non-Fully Depleted SOI CMOS Circuits, Proceedings 1994 IEEE International SOI Conference, Oct. 1994.
Dongwook Suh, et al., Dynamic Floating-Body Instabilities in Partially Depleted SOI CMOS Circuits, 1994 IEEE, pp. 27.6.1-27.6.4.
J. G. Fossum, et al., Floating-Body Problems and Benefis in Fully Depleted SOI CMOS VLSI Circuits, 1991 IEEE, pp. 12.1.1-12.1.4.
Makoto Yoshimi, et al., Technology Trends of Silicon-on-Insulator--Its Advantages and Problems to be Solved--, 1994 IEEE, pp. 17.1.1-17.1.4.
Jacques Gautier, et al., Body Charge Related Transient Effects in Floating Body SOI NMOSFETt's, 1995 IEEE, pp. 26.1.1-26.1.4.
Dongwook Suh, et al., A Physical Charge-Based Model for Non-Fully Depleted SOI MOSFET'sand Its Use in Assessing Floating-Body Effects in SOI CMOS Circuits, Apr. 1995 IEEE Transactions on Electron Devices, vol. 42, No. 4.

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