Circuit and methods for eliminating skew between signals in...

Details Circuit and methods for eliminating skew between signals in... Circuit and methods for eliminating skew between signals in...

2007-06-29

2009-06-02

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233110, C365S222000, C365S194000

Reexamination Certificate

active

07542372

ABSTRACT:
A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.

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patent: 2005/0138277 (2005-06-01), Koo
patent: 2000-0056166 (2000-09-01), None
patent: 2003-0045264 (2003-06-01), None

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