Circuit and method to implement a least recently used cache set

Details Circuit and method to implement a least recently used cache set Circuit and method to implement a least recently used cache set

1996-04-29

1998-12-01

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711128, G06F 1212

Patent

active

058453202

ABSTRACT:
A circuit for controlling which set of a four-way set associated cache memory receives data for storage includes a memory array for storing six bits of information representative of the relative use of the four sets within the cache memory. Least recently used (LRU) update logic operates in conjunction with bit write drivers to generate and write the six bits of information to the memory array in a single access cycle. Replace logic reads the stored information from the memory means and produces output signals therefrom. The output signals are used to control into which of the four sets data is written. Error detection and fault tolerant embodiments are also disclosed as is a method of controlling which set of a four-way set associative cache memory receives data for storage.

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