Static information storage and retrieval – Addressing – Sync/clocking
Patent
1996-12-30
1998-04-28
Dinh, Son T.
Static information storage and retrieval
Addressing
Sync/clocking
365201, G11C 700
Patent
active
057454302
ABSTRACT:
A circuit and method of using a test mode to control the timing of an internal signal using an external control in an integrated circuit. The test mode is designed such that the timing of the internal signal is derived from the external control which can be arbitrarily controlled by a tester. The external signal can be applied to an existing pin for chip control, provided that there is no conflict between the test mode and the operation of the integrated circuit.
REFERENCES:
patent: 5270977 (1993-12-01), Iwamoto et al.
patent: 5579270 (1996-11-01), Yamazaki
patent: 5627838 (1997-05-01), Lin et al.
Kirihata Toshiaki
Krsnik Bozidar
Wong Hing
Chin Dexter K.
Dinh Son T.
International Business Machines - Corporation
Siemens Aktiengesellschaft
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