Circuit and method of testing a fail in a memory device

Details Circuit and method of testing a fail in a memory device Circuit and method of testing a fail in a memory device

2007-05-25

2009-06-09

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S185120, C365S185090, C365S185180

Reexamination Certificate

active

07545692

ABSTRACT:
A circuit for testing a fail in a memory device is disclosed. The memory device includes a memory cell array, a page buffer section, a current controller, and a current measuring section. The memory cell array has memory cells coupled to pairs of bit lines and word lines. The page buffer section has page buffers for programming data to a memory cell selected in accordance with each of the pairs of the bit lines or reading data from the memory cell. The current controller has switching sections coupled to each of the page buffers in the page buffer section and for outputting a current passing through the page buffer selected in accordance with control signals. The current measuring section converts values of currents passing through the switching sections of the current controller into digital values, and outputs the digital values.

REFERENCES:
patent: 6377507 (2002-04-01), Tsao
patent: 09-101347 (1997-04-01), None
patent: 1020010027544 (2001-04-01), None

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