Circuit and method of erasing a nonvolatile semiconductor memory

Details Circuit and method of erasing a nonvolatile semiconductor memory Circuit and method of erasing a nonvolatile semiconductor memory

1998-10-27

1999-11-23

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518524, G11C 1604

Patent

active

059912030

ABSTRACT:
A system capable of stabilizing a tight distribution of threshold voltages of erased flash EEPROM memory cells within a fast time period includes at least one memory cell having source, channel and drain regions on a semiconductor substrate, a floating gate over the channel region on a tunnel oxide layer and a control gate over the floating gate, and a circuit for converging the threshold voltage of an erased memory cell to within a predetermined voltage range. The circuit includes: a driving circuit for applying a first voltage to the control gate and a second voltage between the source and drain regions during the self-convergence operation; and a backbias generator for applying a backbias voltage to the substrate so as to generate hot electrons/holes in the channel region and to inject ones of the hot electrons/holes into the floating gate during the self-convergence operation.

REFERENCES:
patent: 4432075 (1984-02-01), Eitan
patent: 5295107 (1994-03-01), Okazawa et al.
patent: 5511022 (1996-04-01), Yim et al.
patent: 5521867 (1996-05-01), Chen et al.
patent: 5557565 (1996-09-01), Kaya et al.
IEEE Tech. Dig. IEDM, pp. 307-310, 1991, "A Self-Convergence Erasing Scheme For A Simple Stacked Gate Flash Eeprom". Sep., 1991.

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