Circuit and method of controlling cache memory

Details Circuit and method of controlling cache memory Circuit and method of controlling cache memory

1999-03-24

2001-08-21

Yoo, Do Hyun (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S105000, C711S209000, C711S003000

Reexamination Certificate

active

06279083

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates in general to computing systems and, more particularly, to a memory controller that restricts the type of memory device that is cached.
Many modern computer systems use cache memory to speed up storage and retrieval operations. A cache comprises two small blocks of fast access memory. The main block is used to store data, the other is used to store part of the address associated with the data. When the system performs an access to a standard memory (RAM or ROM) the transmitted data may be temporarily stored in the cache. If a subsequent transaction is directed to the same location as the previous one, then the desired data may exist in the cache. Since data transfers from the cache are typically much faster than from standard memory, the overall data transfer rate increases.
The person writing or coding system software designates blocks of storage locations (memory) as cacheable or non-cacheable. If a location is classified as cacheable, then for any read of that location, the microprocessor first checks if the data is held in the cache. The data includes instructions, addresses, alpha-numeric values, etc. If the data is held in the cache, then the data is read from the cache. If the data is not held in the cache, then the data is fetched from the addressed location in the standard memory. Usually, but depending on the cache storage algorithm employed, this data and an associated address field are also placed in the cache. If the memory location is marked as non-cacheable, then all requests are directed to the memory location. For most, if not all, prior art cache controllers, all locations within an address range marked cacheable will be operated on identically. That is, if a location is marked cacheable and its data is not held in the cache, then designated types of accesses made to that location will always result in the data being stored in the cache. No allowance is made for the structure of the accessed memory or the history of previous accesses.
Hence, a need exists for a memory controller that selectively caches based on the access history and the structure of the cached memory.


REFERENCES:
patent: 5157774 (1992-10-01), Culley
patent: 5214610 (1993-05-01), Houston
patent: 5265236 (1993-11-01), Mehring et al.
patent: 5664148 (1997-09-01), Mulla et al.

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