Circuit and method of configuring a field programmable gate arra

Details Circuit and method of configuring a field programmable gate arra Circuit and method of configuring a field programmable gate arra

1995-01-31

1996-02-20

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 40, 364716, H03K 19177

Patent

active

054932394

ABSTRACT:
A field programmable gate array (FPGA) configuration circuit reads configuration data from a memory (12) and converts the parallel data to a serial data stream through a shift register (16) clocked by a clock signal. A first FPGA (18) controls the serial data stream by providing the clock signal when enabled by a start signal. Once the configuration data has been completely loaded into the first FPGA, the first FPGA outputs a done signal to a second FPGA (20) to enable it's clock to control the serial data stream into the second FPGA. The clock from the first FPGA is disabled. Each FPGA passes control to the next FPGA in a daisy chain arrangement by enabling the clock source from the next FPGA while disabling the clock source from previous FPGA as each finishes loading its configuration data.

REFERENCES:
patent: 4870302 (1989-09-01), Freeman
patent: 4930107 (1990-05-01), Chan et al.
patent: 4940909 (1990-07-01), Mulder et al.
patent: 5394031 (1995-02-01), Britton et al.

Affiliated with

Also associated with

Rating

Circuit and method of configuring a field programmable gate arra does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit and method of configuring a field programmable gate arra, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method of configuring a field programmable gate arra will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1358379