Static information storage and retrieval – Read/write circuit – Including signal comparison
Reexamination Certificate
2003-01-27
2004-09-21
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including signal comparison
C365S210130, C365S185200
Reexamination Certificate
active
06795350
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a sense circuit and method for a nonvolatile memory, and more particularly to a circuit and method for tuning a reference bit line loading to a sense amplifier by optionally cutting a capacitive reference bit line.
BACKGROUND OF THE INVENTION
Nonvolatile memories such as electrically erasable programmable read only memory (EEROM) and flash memory are well known. Each of them includes a memory array consisting of a plurality of memory cells and corresponding peripheral circuitry to select one memory cell from the memory array and read out the electrical signal representative of data stored in the selected memory cell. For read-out of stored data from the selected memory cell, a sense amplifier is used to sense the electrical signal during a predetermined timing and to further determine the logic content of the electrical signal, which is also well known.
Generally, a sense amplifier determines the logic value stored in a selected memory cell by comparing the output of the memory cell with a reference signal provided by a reference cell. In order for a sense amplifier to accurately sense the data stored in the memory cell, the reference cell is designed to have the same structure as that of the memory cell and to be fabricated by the same process as that used to fabricate the memory cell to thereby render the operation of the reference cell as similar as possible to that of the memory cell. Nevertheless, variations between memories from the implementations of them by integrated circuits become more significant to their electrical performance as scaling down of integrated circuits progresses, resulting in possible errors occurring in the adjustment or operation of the memory circuits. Conventionally, wiring similated to the electrical path of the memory cell is further introduced to be connected to the reference side of the sense amplifier to reduce the variations of the capacitive effect resulting from the wiring for the memory cells in the integrated circuits, in addition to the aforementioned similation of the reference cell to the memory cell. For example, dummy bit lines or reference bit lines similated to the memory cell bit lines are proposed to be connected to the reference cell by Eitan et al. in U.S. Pat. No. 6,128,226. However, constant reference bit lines cannot be adaptive to various parasitic effects in applications of even a same integrated circuit. In particular, for a sense circuit applied to memories of different density or capacity, a constant ratio for the voltage sense of the sense circuit is impossible to be maintained due to the loading changes on the reference data line node and, as a result, adjustment is made to each circuit for a better voltage sense scheme. Consequently, tedious work or adjustment procedure for the whole circuit cannot be avoid in different applications of the same circuit scheme, even a same sense circuit is used. Therefore, it is desired a tunable reference bit line loading for voltage sense of a sense amplifier adaptive to memories of various capacity or density.
SUMMARY OF THE INVENTION
One object of the present invention is to propose a circuit and method for tuning the reference bit line loading to a sense amplifier adaptive to the voltage sense of memory arrays of different capacity or density.
In a nonvolatile memory, a sense amplifier compares the voltage on a sense node with the voltage on a reference data line node to determine a sensing signal, of which the sense node is selectively connected to a memory cell to produce a voltage representative of data stored in the memory cell on the sense node. According to the present invention, a circuit and method for tuning a reference bit line loading comprises connecting a reference cell unit and a reference bit line unit to a reference bit line node that is controlled to be connected to the reference data line node, in which the reference cell unit includes at least one reference cell to provide a reference current to the reference bit line node and the reference bit line unit includes at least one reference bit line optionally cut to determine the reference bit line loading. Preferably, the reference cell unit includes a plurality of identical reference cells connected in parallel, each generates a reference bit current, and the reference bit line unit includes a plurality of reference bit lines each having a same capacitance before being cut. The number of the reference cells is preferred equal to the number of the reference bit lines.
REFERENCES:
patent: 5828616 (1998-10-01), Bauer et al.
patent: 6330188 (2001-12-01), Pascucci
patent: 6362661 (2002-03-01), Park
patent: 6404677 (2002-06-01), Lee
Chen Han-Sung
Hung Chun-Hsiung
Liao Kuo-Yu
Po Chen-Hao
Hoang Huan
Macronix International Co. Ltd.
Rabin & Berdo P.C.
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