Circuit and method for testing a data memory

Details Circuit and method for testing a data memory Circuit and method for testing a data memory

2005-11-22

2005-11-22

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

06968483

ABSTRACT:
A data memory to be tested is connected to a processing unit. Data items to be stored are produced from a test pattern data item in the processing unit and are stored in the data memory. The data memory is tested in that the test pattern data items are received from a test device, processed using a first function to form data items to be stored, and the data items are then stored. After the stored data items are read from the memory they are processed with a second function to form test data items whose number is once more smaller than the stored data items that are read from the memory.

REFERENCES:
patent: 6085346 (2000-07-01), Lepejian et al.
patent: 6195771 (2001-02-01), Tanabe et al.
patent: 6477673 (2002-11-01), Ferrant et al.
patent: 6691271 (2004-02-01), Kanehira et al.
patent: EP 0 828 257 (1998-03-01), None
Tadahiko Sugibayashi et al,.: “A Distributive Serial Multi-Bit Parallel Test Scheme for Large Capacity DRAMs”, IEICE Trans. Electron., vol. E77-C, No. 8, Aug. 1994, pp. 1323-1327.

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