Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2000-06-30
2001-06-12
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S190000, C365S228000, C365S226000, C365S236000, C365S233100
Reexamination Certificate
active
06246603
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a ferroelectric memory device, and particularly to a circuit and method for providing a ferroelectric memory device having reduced imprint effects.
2. Background of the Invention
Ferroelectricity is a phenomenon which can be observed in a relatively small class of dielectrics called ferroelectric materials. In a normal dielectric, upon the application of an electric field, positive and negative charges will be displaced from their original position—a concept which is characterized by the dipole moment or polarization. This polarization or displacement will vanish, however, when the electric field returns back to zero. In a ferroelectric material, on the other hand, there is a spontaneous polarization—a displacement which is inherent to the crystal structure of the material and does not disappear in the absence of the electric field. In addition, the direction of this polarization can be reversed or reoriented by applying an appropriate electric field.
These characteristics result in ferroelectric capacitors, formed from ferroelectric film or material disposed between parallel conduction plates, being capable of storing in a nonvolatile manner a first charge corresponding to a first polarization state in which the direction of polarization is in a first direction, and a second charge corresponding to a second polarization state in which the direction of polarization is in a second direction opposite the first direction. Ferroelectric capacitors are utilized in nonvolatile random access memory devices having a memory cell array architecture that is similar to the memory cell array architecture of dynamic random access memory (DRAM) devices.
In general terms, there are two types of ferroelectric memory cells. Referring to
FIG. 1A
, a one transistor, one capacitor (1T1C) memory cell utilizes a pass gate transistor T connected between a bit line B and a first plate of ferroelectric capacitor C. A second plate of ferroelectric capacitor C is connected to a plate line P. The gate terminal of pass gate transistor T is connected to a word line W. A memory device utilizing a 1T1C memory cell uses a reference memory cell that is accessed at the same time the 1T1C memory cell is accessed so as to provide a charge differential appearing across a pair of bit lines coupled to the 1T1C cell and the reference cell. The use of 1T1C ferroelectric memory cells is known in the art.
Referring to
FIG. 1B
, a two transistor, two capacitor (2T2C) memory cell includes two ferroelectric capacitors C
1
and C
2
. A first pass gate transistor T
1
is connected between a first plate of ferroelectric capacitor C
1
and a first bit line BL of a bit line pair. A second pass gate transistor T
2
is connected between a first plate of ferroelectric capacitor C
2
and a second bit line BL′ of the bit line pair. A second plate of ferroelectric capacitors C
1
and C
2
is connected to a plate line P. The gate terminal of pass gate transistors T
1
and T
2
is connected to the word line W. Each capacitor C
1
and C
2
stores a charge representative of the polarization state thereof, the charge combining with the charge of the other capacitor to result in a charge differential appearing across bit lines BL and BL′ when the 2T2C memory cell is accessed. The polarity of the charge differential denotes the binary value stored by the 2T2C memory cell. The use of 2T2C ferroelectric memory cells is known in the art.
A problem with ferroelectric memory devices is the existence of a phenomenon known as imprint. Imprint is a characteristic of ferroelectric films that refers to the tendency of a ferroelectric film/capacitor to prefer one polarization state over another polarization state. Imprint is known to occur when a ferroelectric capacitor is maintained in a single polarization state for a prolonged period of time. Imprint adversely effects the ability of a ferroelectric capacitor to switch between the polarization states. Consequently, the existence of imprint may directly impact the performance of a ferroelectric memory device.
SUMMARY OF THE INVENTION
The present invention overcomes the shortcomings in prior systems and thereby satisfies a significant need for a ferroelectric memory device having reduced imprint effects. In accordance with an embodiment of the present invention, there is disclosed a ferroelectric memory device, including a plurality of ferroelectric memory cells and circuitry for conditioning or logically inverting the data value stored in each ferroelectric memory cell following an occurrence of at least one predetermined time and during a period when the ferroelectric memory device is not being accessed. By somewhat regularly inverting the data stored in the ferroelectric memory device and inverting the data read from and to be written to the ferroelectric memory device during the time the stored data is inverted, the occurrence of imprint is substantially reduced while maintaining integrity of the stored data.
REFERENCES:
patent: 6008659 (1999-12-01), Traynor
Galanthay Theodore E.
Jorgenson Lisa K.
STMicroelectronics Inc.
Szuwalski Andre
Tran Andrew Q.
LandOfFree
Circuit and method for substantially preventing imprint... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit and method for substantially preventing imprint..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for substantially preventing imprint... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2470969