Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-09-17
2002-12-31
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S154000
Reexamination Certificate
active
06501692
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of memory devices in integrated circuits, and more particularly, the present invention relates to circuits and method for testing memory cells in such memory devices. More specifically, the present invention relates to a method and circuit for stress testing a memory cell of a static random access memory (SRAM) device.
2. Description of Related Art
A typical static random access memory (SRAM) circuit has arrays of memory cells that include word lines, a read/write circuit coupled to each array, and an access control circuit. The read/write circuit provides the capability of writing data or bit values to each memory cell. The access control circuit drives a plurality of word lines to perform read and write operations. Each memory cell has a pair of cross-coupled inverters that are utilized to store a digital value (e.g., a high value or a low value). For a memory cell of the SRAM circuit, a circuit path along one of the cross-coupled inverters holds the digital value and typically includes a first p-type transistor, a first n-type transistor, and a first pass-gate transistor. Another circuit path along another one of the cross-coupled inverters usually holds the complementary digital value and has a second p-type transistor, a second n-type transistor, and a second pass-gate transistor. The pass gate transistors are used to couple the two cross-coupled inverters to a bit line and a complementary bit line of the SRAM cell. Therefore, one SRAM circuit path generally maintains the digital value while another SRAM circuit path generally maintains the complementary digital value.
The SRAM circuit is generally made as an integrated circuit (IC) according to an integrated circuit process. The IC process involves the formation of semiconductor and metal structures for the SRAM circuit. Diffusion regions and polysilicon structures within the semiconductor structures typically form the transistors of the SRAM circuit. Metal structures are utilized to provide electrical connections between the transistors and other components of the SRAM circuit. The typical IC process involves the formation of numerous electrical contacts for each memory cell, and the contacts may be formed where diffusion regions, polysilicon structures, metal interconnecting structures, and/or vias of the transistors meet.
However, the typical IC involves defects occurring in the semiconductor and metal structures during the IC manufacturing and fabrication process. For example, the defects in IC fabrication process may exist and cause “weak” contacts or failures in the memory cells or in the individual transistors of the memory cells. Two types of defects generally exist for a memory cell: a symmetric defect or an asymmetric defect. A symmetric defect impairs the performance of the pair of cross-coupled inverters of a memory cell while an asymmetric defect impairs only one of the cross-coupled inverters. For example, a defective contact in a power supply line, which supplies power to the entire memory cell, is considered a symmetric defect since the pair of cross-coupled inverters is denied power. A defect in a p-transistor within one of the cross-coupled inverters is an example of an asymmetric defect since the defect only affects one of the cross-coupled inverters.
Various testing procedures exist to test the quality of the IC and to detect defects in the IC with the SRAM circuit. One such test is to place the IC having the SRAM circuit into a specialized IC tester. The IC tester writes data into the SRAM circuit and immediately reads the data therefrom to verify the data stored therein. If the data read from the SRAM circuit does not match the data written to the SRAM circuit, then the SRAM circuit is deemed defective. This type of test procedure, however, does not detect manufacturing defects of the memory cell that cause data retention problems that occur over a relatively long period of time. For example, a memory cell for the SRAM device having a defective p-transistor within one of the cross-coupled inverters may be able to retain a high voltage value for only a short time period. The high voltage maintained at the nodes of the memory cell would discharge through diffusion regions of the transistors of the memory cell. A defective p-transistor would then be able to maintain the high voltage for a short time period but would not be able to maintain the high voltage level for a long period of time.
One known way of detecting such data retention defects is to provide the IC tester with a delay that is long enough to allow such a defective memory cell to discharge. However, the time between when the IC tester writes the data and reads the data is increased so that the data retention defects are detectable. Such delays significantly increase the testing time of each IC. Multiple IC testers would then have to be used in parallel to decrease the overall testing time of all the ICs, but the use of multiple IC testers, which are relatively expensive, increase the overall costs of manufacturing and testing the ICs with SRAM devices.
Another prior art method of testing ICs having SRAM circuits involves coupling a “weak write” test circuit to each array of memory cells. The “weak write” test generally involves using a separate test circuit for applying a pre-determined voltage amount to the memory cell to test the existence of excess resistance or leakage within the transistors and transistor paths of the memory cell. The pre-determined voltage amount is set at a value in which the applied voltage will not affect the value of a good memory cell but will change the value of a defective memory cell. U.S. Pat. No. 5,559,745 to Banik et al. (“Banik”) assigned to Intel Corporation, Santa Clara, Calif., discloses such an exemplary “weak write” circuit and method.
Prior art
FIG. 1
shows a memory cell
16
being tested by a “weak write” test circuit
18
according to Banik. Memory cell
16
is a typical SRAM cell that includes a plurality of transistors T
1
to T
6
configured in a manner to form cross-coupled inverters as shown in prior art FIG.
1
. Fabrication defects in the transistor(s) or along the transistor path(s) may reduce the strength of pull-up p-type transistors T
1
and T
2
and/or the pull-down n-type transistors T
3
and T
4
, and these defects are a potential source of data retention defects. Other types of fabrication defects are from leakage paths at node N
1
and/or node N
2
, which may also be potential sources of data retention defects. Bit line pair
8
consists of a bit line
10
and a complementary bit line, bit bar line
12
, as shown in prior art FIG.
1
. Transistor T
5
is a pass gate transistor, which couples a node NI to bit line
10
. Transistor T
5
is also coupled to word line (“WL”)
14
. Similarly, the transistor T
6
is another pass gate transistor that connects a node N
2
to bit bar line
12
. Transistor T
6
is also coupled to word line (“WL”)
14
. Transistors T
5
and T
6
and, in turn, memory cell
16
are activated by word line
14
.
Various contacts, such as contacts CA to CJ, exist in circuit paths of memory cell
16
. Defects may exist or be generated from contacts, such as contacts CA to CJ, in memory cell
16
. Defective contacts may result in the necessary or proper connection not being provided between the integrated circuit structures or may provide a highly resistive connection compared to other contacts. The lack of proper connections and/or the existence of highly resistive connections may cause long-term data retention problems for memory cell
16
.
“Weak write” test circuit
18
requires the passing of two separate tests in order to verify whether memory cell
16
is not defective. The first test is the weak writing of a zero (“0”) digital value into memory cell
16
. A one (“1”) digital value is first written into memory cell
16
. “Weak write” test circuit
18
is then activated to attempt to weak write a zero (“0”) digital value into memory cell
16
. The digital value of
Jensen Robert A.
Melanson John L.
Pantelakis Dimitris
Shenoy Vikram
Cirrus Logic Inc.
Elms Richard
Lin, Esq. Steven
Phung Anh
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