Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2001-03-28
2004-03-16
Baderman, Scott (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
06708295
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a failure analysis memory used for analyzing a failure of a device, in particular to a circuit and a method, for storing data prior to and after determining the failure of the device.
2. Description of Related Art
A failure analysis memory used for analyzing a failure of a device is a circuit for storing such data as an address, a data and so on at the real time of determining the failure of the device, when being triggered by the failure signal from the device. For example, the failure analysis memory is a circuit used in a burn-in tester.
The burn-in tester is a semiconductor testing apparatus for electrically testing a device under the temperature-stress. The burn-in tester comprises a thermostatic chamber wherein a temperature thereof and an electric signal thereof can be programmed and a plurality of burn-in boards on which devices under test are mounted can be contained. The burn-in tester and the burn-in boards are connected to each other through a connecter, to transmit and receive various electric signals between them. Therefore, the burn-in tester tests each of burn-in boards according to each burn-in board.
FIG. 3
shows a structure of a circuit
2
for storing data prior to and after determining a failure of a device, according to an earlier development. In
FIG. 3
, the circuit
2
comprises a device under test
10
, a comparing circuit
11
, an address generating circuit
12
, a data generating circuit
13
, a counter
21
, an address pointer circuit
22
, a shift circuit
23
, a read-out control circuit
24
, a memory circuit
25
and a controller
30
.
The device under test
10
outputs an output signal, and the data generating device
13
outputs an expected value signal. The comparing circuit
11
compares the output signal with the expected value signal, to determine the pass or the failure of the device under test
10
. When the comparing circuit
11
determines the failure of the device under test
10
, the counter
21
counts up the number of data stored prior to determining the failure of the device and the number of data stored after determining the failure of the device, and outputs an effective WE (Write Enable) signal to a WE terminal of the memory circuit
25
every counting up. Thereafter, the memory circuit
25
stores data signals inputted to a data pin (I/O) to an address space thereof indicated by an address pointer signal inputted to an address (ADD) terminal.
The address pointer signal to be inputted to the ADD terminal of the memory circuit
25
is generated by the address pointer circuit
22
. That is, when the address pointer circuit
22
receives the WE signal outputted from the counter
21
, the address pointer circuit
22
counts up an address pointer every counting, to generate the address pointer signal. Therefore, the address pointer circuit
55
outputs the address pointer signal generated to the ADD terminal of the memory circuit
22
.
The data signal to be inputted to the I/O terminal of the memory circuit
25
comprises, for example, an address signal outputted from the address generating circuit
12
, the expected value signal outputted from the data generating circuit
13
, and the output signal outputted from the device under test
10
. Further, the data signal is inputted to the I/O terminal through a bus
40
and the shift circuit
23
composed of shift registers corresponding to the number of data stored prior to determining the failure of the device under test
10
.
Because a reference clock signal is inputted to both the counter
21
and the shift circuit
23
, the data signal outputted from the shift circuit
23
is inputted to the I/O terminal of the memory circuit
25
later than the time wherein the WE signal outputted from the counter
21
is inputted to the WE terminal of the memory circuit
25
by the time corresponding to the number of steps of the shift registers contained in the shift circuit
23
. Accordingly, it is possible that the memory circuit
25
stores the data prior to determining the failure of the device under test
10
, therein.
The data stored in the memory circuit
25
is read out according as the read-out control circuit
24
controls and outputs an OE (Output Enable) signal to an OE terminal of the memory circuit
25
. That is, when the effective OE signal outputted from the read-out control circuit
24
is inputted to the OE terminal of the memory circuit
25
, the memory circuit
25
outputs the data stored therein from the I/O terminal, and after, the controller
30
stores the data therein. Therefore, an operator analyzes the device under test
10
on the basis of the data stored in the controller
30
.
However, because the circuit
2
for storing data prior to and after determining the failure of the device, as show in
FIG. 3
, according to an earlier development, uses the shift register for holding the data prior to determining the failure of the device, it is necessary that the circuit
2
comprises the shift registers corresponding to the number of data to be stored prior to determining the failure. As a result, in the case wherein there are a lot of data to be stored prior to determining the failure of the device or there are a lot of data stored prior to determining the failure of the device, there has been programs wherein the step number of the shift registers contained in the shift circuit
23
increases extremely and the shift circuit
23
has a more complex structure.
SUMMARY OF THE INVENTION
The present invention was developed in order to solve the problems as mentioned above.
An object of the present invention is to provide a circuit and a method, which can easily store data prior to and after determining a failure of a device without using a shift circuit being under the control of a number of data prior to determining the failure of the device.
In accordance with the first aspect of the present invention, a circuit (for example, a circuit
1
shown in
FIG. 1
) for storing data prior to and after determining a failure of a device, comprises: a counter (for example, a counter
51
shown in
FIG. 1
) for always enabling a memory (for example, a memory circuit
55
shown in
FIG. 1
) which stores data prior to and after determining a failure of a device, to write the data prior to determining the failure of the device, before the device is determined as the failure, and for disabling the memory from writing any data on the basis of the number of the data prior to and after determining the failure, after the device is determined as the failure; a first address pointer circuit (for example, an address pointer
1
circuit
52
shown in
FIG. 1
) for controlling the memory so as to always store the data prior to determining the failure of the device in a predetermined address space thereof, until the device is determined as the failure, and for holding an address pointer indicating the predetermined address space wherein the data prior to determining the failure of the device is stored, when the device is determined as the failure; and a second address pointer circuit (for example, an address pointer
2
circuit
53
shown in
FIG. 1
) for controlling the memory so as to store the data after determining the failure of the device in a predetermined address space thereof other than the predetermined address space wherein the data prior to determining the failure of the device is stored, after the device is determined as the failure.
In accordance with the second aspect of the present invention, a method of storing data prior to and after determining a failure of a device, comprises: a memory control step of always enabling a memory which stores data prior to and after determining a failure of a device, to write the data prior to determining the failure of the device, before the device is determined as the failure, and of disabling the memory from writing any data on the basis of the number of the data prior to and after determining the failure, after the device is determined as the failure; a first
Ando Electric Co. Ltd.
Baderman Scott
Oliff & Berridg,e PLC
LandOfFree
Circuit and method, for storing data prior to and after... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit and method, for storing data prior to and after..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method, for storing data prior to and after... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3270792