Electronic digital logic circuitry – Multifunctional or programmable
Patent
1996-11-27
2000-03-14
Santamauro, Jon
Electronic digital logic circuitry
Multifunctional or programmable
327407, 327525, H03K 19173
Patent
active
060377992
ABSTRACT:
A multiplexing circuit includes a reference terminal, a plurality of multiplexing input terminals, and a buffer having an input terminal and an output terminal. The multiplexing circuit also includes a plurality of first elements that each have a programmable conductivity and that are each serially coupled between a corresponding one of the multiplexing input terminals and the input terminal of the buffer. When one of the input signals is to be coupled to the multiplexer output terminal, the element corresponding to the selected input signal is programmed in a conductive state, and the remaining elements are programmed in a nonconductive state. When none of the input signals are selected, each element is programmed in a conductive state and the input signals each have the same value so as to prevent signal conflicts and short circuits at nodes within the multiplexing circuit.
REFERENCES:
patent: 4228528 (1980-10-01), Cenker et al.
patent: 4573146 (1986-02-01), Graham et al.
patent: 4601019 (1986-07-01), Shah et al.
patent: 4656610 (1987-04-01), Yoshida et al.
patent: 4689494 (1987-08-01), Chen et al.
patent: 4714839 (1987-12-01), Chung
patent: 4734889 (1988-03-01), Mashiko et al.
patent: 4791615 (1988-12-01), Pelley, III et al.
patent: 4829480 (1989-05-01), Seo
patent: 4833652 (1989-05-01), Isobe et al.
patent: 4837747 (1989-06-01), Dosaka et al.
patent: 4985866 (1991-01-01), Nakaizuri
patent: 5034925 (1991-07-01), Kato
patent: 5058059 (1991-10-01), Matsuo et al.
patent: 5107464 (1992-04-01), Sahara et al.
patent: 5124948 (1992-06-01), Takazawa et al.
patent: 5146429 (1992-09-01), Kawai et al.
patent: 5177743 (1993-01-01), Shinoda et al.
patent: 5195057 (1993-03-01), Kasa et al.
patent: 5233233 (1993-08-01), Inoue et al.
patent: 5257229 (1993-10-01), McClure et al.
patent: 5262994 (1993-11-01), McClure
patent: 5281868 (1994-01-01), Morgan
patent: 5293339 (1994-03-01), Suzuki et al.
patent: 5295102 (1994-03-01), McClure
patent: 5299164 (1994-03-01), Takeuchi et al.
patent: 5307316 (1994-04-01), Takemae
patent: 5311472 (1994-05-01), Ota
patent: 5337278 (1994-08-01), Cho
patent: 5355340 (1994-10-01), Coker et al.
patent: 5377146 (1994-12-01), Reddy et al.
patent: 5381370 (1995-01-01), Lacey et al.
patent: 5455798 (1995-10-01), McClure
patent: 5471426 (1995-11-01), McClure
patent: 5572470 (1996-11-01), McClure et al.
patent: 5574688 (1996-11-01), McClure et al.
patent: 5598114 (1997-01-01), Jamshidi
patent: 5608678 (1997-03-01), Lysinger
Nishimura et al., "A Redundancy Test-Time Reduction Technique in 1-Mbit DRAM with a Multibit Test Mode," IEEE Journal of Solid-State Circuits24(1):43-49, 1989.
Kayano et al., "25-ns 256K .times. 1/164K .times. 4 CMOS SRAM's," IEEE Journal of Solid-State Circuits SC-21(5):686-690, 1986.
Childs et al., "An 18 ns 4K .times. 4 CMOS SRAM," IEEE Journal of Solid-State Circuits SC-19(5):545-551, 1984.
Sakurai et al., "A Low Power 46 ns 256 kbit CMOS Static Ram with Dynamic Double Word Line," IEEE Journal of Solid-State Circuits SC-19(5):578-585, 1984.
Hardee et al., A Fault-Tolerant 20 ns/375 mW 16K .times. 1 NMOS Static Ram, IEEE Journal of Solid-State Circuits SC-16(5):435-443, 1981.
Carlson David V.
Galanthay Theodore E.
Jorgenson Lisa K.
Santamauro Jon
STMicroelectronics Inc.
LandOfFree
Circuit and method for selecting a signal does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit and method for selecting a signal, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for selecting a signal will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-173034