Circuit and method for replacement of address translations

Details Circuit and method for replacement of address translations Circuit and method for replacement of address translations

1999-11-08

2000-08-15

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711207, G06F 1212

Patent

active

061051101

ABSTRACT:
A circuit used to control the modification of content within memory implemented within an address translation unit. This memory includes a plurality of entries which contain virtual and physical addresses associated with an address translation. The circuit includes an update control circuit coupled to the address translation circuit. The update circuit is configured to set an entry to an invalid state or point to an entry to be loaded with a new address translation. The circuit further includes a flush control circuit that is configured to control the update control circuit. Such control includes setting an entry to an invalid state upon detecting a particular event.

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"Integrated Memory Management for the MC68030", Kirk Holden and Steve McMahan, Motorola, Inc., Microprocessor Products Group (OE38), pp. 586-589 .

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