Circuit and method for reliably performing bus reset...

Details Circuit and method for reliably performing bus reset... Circuit and method for reliably performing bus reset...

2000-06-22

2003-03-04

Dharia, Rupal (Department: 2189)

Electrical computers and digital data processing systems: input/

Intrasystem connection

C710S104000, C710S105000, C710S106000, C713S500000, C713S600000, C713S601000

Reexamination Certificate

active

06529977

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to transmission and reception of signals between devices (nodes) attached to a computer over a serial bus such as the IEEE-1394 bus specified according to the IEEE-1394 Standard for a High Performance Serial Bus (or IEEE Std 1394-1995).
2. Description of the Related Art
The IEEE 1394 standard specifies protocols for the transmission and reception of various control signals and communication signals between peripheral devices of a computer such as printers, hard disk drives, scanners, digital cameras (nodes) at different layers of each node connected to a serial bus. For the physical layer of each node, a procedure is specified for bus initialization and determination of bus ownership. This procedure is described by a state machine having four broadly classified functions. The bus initialization procedure consists of three network initialization processes (Bus Reset process, Tree ID process, and Self ID process) and a Normal process (for normal communication between nodes).
For each of these processes a number of states are defined. For Bus Reset process, states R
0
(Reset Start) and R
1
(Reset Wait) are defined, and for Tree ID process states T
0
(Tree ID start), T
1
(Child Handshake), T
2
(Parent Handshake) and T
3
(Root Contention) are defined. Similarly, five states are defined for Self ID process, including S
0
(Self ID Start), S
1
(Self ID Grant), S
2
(Self ID Receive), S
3
(Send Speed Capabilities) and S
4
(Self ID Transmit), and six states are defined for Normal process, including A
0
(Idle), A
1
(Request), A
2
(Grant), TX (Transmit), RX (Receive) and PH (PHY Response). The present invention is primarily concerned with the operation of the Bus Reset process.
Two bus reset processes are defined by the IEEE-1394 standard (P1394a Draft Standard for a High Performance Serial Bus (Supplement), Draft 2.0 Mar. 15, 1998) long bus reset and short bus reset. The cable environment of the standard assumes that the state of the bus is unknown when a bus reset occurs and requires that a reset be long enough to permit all nodes of the bus to receive a long bus reset signal and perform longest transactions within a period of about 166 &mgr;s. Short bus reset is a process in which a node that is performing a bus reset arbitrates for control of the bus prior to asserting reset. The duration of short bus reset is about 1.3 &mgr;s.
In a bus reset process, the operation of a node proceeds according to FIG.
1
. When a node detects a bus reset signal at one of its ports when powered on, or operating in a state other than state RX (=Receive) such as Tree ID, Self ID or Normal process, it changes to state R
0
(=Reset Start) to begin a bus reset process and sets the reset time to the long reset time of 166 &mgr;s. If the node is in state RX when it detects bus reset, it changes to state R
0
and sets the reset time to the short reset time of 1.3 &mgr;s.
In state R
0
, the node asserts a bus reset signal on all of its active ports. When the short reset time of 1.3 &mgr;s expires the node changes to state R
1
(=Reset Wait) in which all ports of the node return bus to idle state. If the node receives an idle or a parent notify signal from all of its active ports before the Reset Wait period of 1.46 ns expires, the state of the node changes to state T
0
(=Tree ID Start) which is the initial state of Tree ID process. If all ports of the node receive no idle state signal nor parent notify signal within a period of 1.46 &mgr;s (=the 1.3-&mgr;short reset time plus the 160-ns reset wait time) from state R
1
, the node returns from state R
1
to state R
0
and sets the reset time to the long reset time of 166 &mgr;s.
In a short bus reset process that proceeds in a four-node network, for example (see FIG.
2
A), a node
1
attempts to gain bus ownership prior to performing a bus reset by asserting a Request signal R(
1
) on one of the ports of a root node
2
that is authorised to assign bus ownership, changing its state from A
0
(=Idle) to A
1
(=Request). In response, the root node
2
returns a Grant signal G(
2
) to node
1
and asserts a Data Prefix signal D(
2
) on its other port, which is repeated by a node
3
as a Data Prefix signal D(
3
) to node
4
. Nodes
3
and
4
change their state from A
0
to RX. Node
1
responds to the Grant signal G(
2
) by changing its state from A
1
to TX (=Transmit). Node
1
FIG. 2B
) changes to R
0
(=Reset Start) by asserting a Data Prefix DP(
4
) followed by a Bus Reset signal and receiving a Bus Reset signal B(
5
) from the root node
2
. The Data Prefix DP(
4
) and the following Bus Reset are repeated by root node
2
as D(
5
) which is repeated by node
3
as D(
6
) to node
4
. Node
3
and
4
return Bus Reset signals B(
6
) and B(
7
) to nodes
2
and
3
, respectively, and change their state from RX to R
0
(=Reset Start) by setting reset time to the short reset time. When all nodes have changed their state to R
1
, nodes
1
,
2
, and
3
assert idle signals I(
8
), I(
9
) and I(
10
), respectively, to start a Tree ID process (FIG.
2
C).
However, if the cable length between two nodes is longer than the 4.5 meter limit of the data-strobe link of the 1394 standard, there is a high likelihood of a bus reset signal from a node arriving on the node at the opposite end of the cable after expiration of the short reset time of 1.3 &mgr;s, even if the source node is performing a short bus reset. Hence, the source node must perform a long bus reset. This is a serious problem for a bus environment in which internodal bus length is more than 50 meters by use of 8B/10B block coding and unshielded twisted pairs or fiber optic links (for further information, see P1394b Draft Standard for a High Performance Serial Bus (Supplement) Draft 0.17, Feb. 5, 1999).
Assume that the nodes
2
and
3
are interconnected by a long-distance cable as shown in FIG.
3
and that node
1
changes from A
0
(=Idle) to A
1
(=Request) by asserting a Request to node
2
, which grants bus ownership and asserts a Data Prefix DP
1
to node
3
. Node
1
shifts to TX by asserting a Data Prefix DP
2
and changes to state R
0
by signalling a Bus Request BR
1
to node
2
, resulting in the node
2
changing to state R
0
by simultaneously asserting a Bus Request BR
2
to nodes
1
and
3
. Node
3
changes its state from RX to R
0
by signalling a Bus Request BR
3
to nodes
2
and
4
. When the short reset period of 1.3 &mgr;s expires at node
2
, it changes state from R
0
to R
1
by signalling an idle state ID
2
to nodes
1
and
3
. Similarly, the short reset time expires at node
2
and it changes from R
0
to R
1
by signaling an idle state ID
3
to nodes
2
and
4
. Root node
2
will change its state from R
1
to R
0
if the critical period of 1.46 &mgr;s expires. Since an idle or a parent notify signal should arrive a 1.46-&mgr;s period after the root node
2
changes to state R
1
in order for it to reliably perform a short bus reset, the idle signal ID
3
must arrive on node
2
within the 1.46-&mgr;s critical period after the short reset period of 1.3 &mgr;s. However, due to the long transmission delay between nodes
2
and
3
, the idle state signal ID
3
arrives on node
2
after the 1.46-&mgr;s critical period and the node
2
changes to state R
0
, rather than T
0
, and sets the bus reset to the long reset time. In order for the node
2
to perform a short bus reset, an idle state or a parent notify state should arrive within a total period of 2.76 &mgr;s after the node
2
asserted Bus Reset BR
2
to node
3
.
In a long-distance cable environment, the maximum turnaround time between two nodes is given by:
2×1.3 &mgr;s+0.16 &mgr;s>2 (cable delay+physical-layer delay)+1.3 &mgr;s
therefore,
1.3 &mgr;s+0.16 &mgr;s>2 (cable delay+physical-layer delay)
If the physical-layer delay is 300 &mgr;s and the cable delay is 5 s/meter, the cable length between two nodes

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