Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2006-02-14
2006-02-14
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S149000, C365S233100
Reexamination Certificate
active
06999369
ABSTRACT:
A circuit for refreshing memory cells of a dynamic memory contains a refresh control circuit (3, 4, 7) and a memory circuit (2) for storing a plurality of register bits (2-1to2-n), a respective one of the register bits being assigned to at least one of the memory cells. In the event of an access to one of the memory cells, a set circuit (6) sets the assigned register bit (2-1to2-n), and a reset circuit (5) resets a set register bit (2-1to2-n). For controlling a refresh operation of one of the memory cells (MC), the refresh control circuit (3, 4, 7) evaluates the assigned register bit (2-1to2-n) and carries out the refresh operation in a manner dependent on the state of said register bit. For a refresh operation that is to be effected, a plurality of the memory cells (MC) are selected in an ascending or descending order of their addresses (x-Adr), and the respectively assigned register bits (2-1to2-n) of the memory cells, for resetting, are selected in an opposite order in a descending or ascending order of their addresses (x-Adr).
REFERENCES:
patent: 3810129 (1974-05-01), Behman et al.
patent: 5890198 (1999-03-01), Pawlowski
patent: 6094705 (2000-07-01), Song
patent: 6388934 (2002-05-01), Tobita
patent: 6483764 (2002-11-01), Chen et al.
patent: 6614704 (2003-09-01), Dobler et al.
patent: 6646944 (2003-11-01), Shimano et al.
patent: 2003/0156483 (2003-08-01), Feurle et al.
patent: 100 57 275 (2002-06-01), None
patent: 102 06 367 (2003-12-01), None
patent: 0 851 427 (1998-07-01), None
patent: 05101650 (1993-04-01), None
patent: 09282873 (1997-10-01), None
patent: WO 98/18130 (1998-04-01), None
patent: WO 00/54159 (2000-09-01), None
patent: WO 02/058072 (2002-07-01), None
“Infineon Technologies and Micron Technology Announce Cooperation to Develop ‘CellularRAM,”’ Joint News Release by Infineon and Micron, Munich, Germany/Boise, Idaho, USA, Jun. 24, 2002.
Ohsawa, T., et al., “Optimizing the DRAM Refresh Count for Merged DRAM/Logic LSIs,” Proceedings of Intenrational Symposium on Low Power Electronics and Design, 1998, pp. 82-87.
Hoang Huan
Slater & Matsil L.L.P.
LandOfFree
Circuit and method for refreshing memory cells of a dynamic... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit and method for refreshing memory cells of a dynamic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for refreshing memory cells of a dynamic... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3681423