Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2006-10-17
2006-10-17
Tran, M. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S227000
Reexamination Certificate
active
07123533
ABSTRACT:
A circuit for refreshing memory cells of a dynamic memory contains a refresh control circuit for driving a memory cell array for accessing memory cells of the dynamic memory for a refresh process. Furthermore, a storage circuit is provided, which is assigned to at least one of the memory cells, for storing a time information item with regard to a last previous access to the assigned memory cell during the operation of the memory, a register bit being set in a manner dependent on the stored time information item and being able to be evaluated for controlling a refresh process. The refresh control circuit calls up the time information item stored in the storage circuit during operation of the memory and accesses the memory cell array in such a way that the memory cell assigned to the storage circuit is refreshed in a manner dependent on the time information item.
REFERENCES:
patent: 3810129 (1974-05-01), Behman et al.
patent: 5890198 (1999-03-01), Pawlowski
patent: 6094705 (2000-07-01), Song
patent: 6167484 (2000-12-01), Boyer et al.
patent: 6205067 (2001-03-01), Tsukude
patent: 6449685 (2002-09-01), Leung
patent: 6483764 (2002-11-01), Chen Hsu et al.
patent: 6614704 (2003-09-01), Dobler et al.
patent: 6690606 (2004-02-01), Lovett et al.
patent: 2003/0156483 (2003-08-01), Feurle et al.
patent: 100 57 275 (2002-06-01), None
patent: 102 06 367 (2003-12-01), None
patent: 0 851 427 (1998-07-01), None
patent: 05101650 (1993-04-01), None
patent: 09282873 (1997-10-01), None
patent: WO 98/18130 (1998-04-01), None
patent: WO 00/54159 (2000-09-01), None
patent: WO 02/058072 (2002-07-01), None
“Infineon Technologies and Micron Technology Announce Cooperation to Develop ‘CellularRAM,’” Joint News Release by Infineon and Micron, Munich, Germany/Boise, Idaho, USA, Jun. 24, 2002.
Ohsawa, T., et al., “Optimizing the DRAM Refresh Count for Merged DRAM/Logic LSIs,” Proceedings of Intenrational Symposium on Low Power Electronics and Design, 1998, pp. 82-87.
Infineon - Technologies AG
Slater & Matsil L.L.P.
Tran M.
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