Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-11-19
2003-09-02
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S201000
Reexamination Certificate
active
06614704
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an apparatus for controlling an information refresh operation in memory cells in a memory module and to a corresponding method in which a periodic sequence of control signals for triggering the information refresh operation is applied to the memory cells.
In dynamic random access memories (DRAMs), it is necessary for the information stored in the memory cells to be periodically refreshed, since the memory cells can retain the information stored in them for only a limited time. The reason for this is that capacitors are used as memory cells for DRAMs. These capacitors discharge themselves after a specific time as a result of unavoidable quiescent currents, so that the stored charges of the capacitors have to be regularly renewed. The memory cells are therefore recharged at fixedly predetermined time intervals, so-called refresh cycles. The pulse for recharging, the so-called refresh pulse, can be generated internally within the module or else externally. In modern DRAMs, refresh cycles of at least 4096 refresh operations per 64 ms (refresh rate 6 k/64 ms) are customary.
The refresh cycle for the DRAM, i.e. the interval between the individual refresh pulses, must be chosen such that even the memory cell with the shortest retention time, which specifies how long the memory content can be retained in the associated cell, is refreshed again in good time. The conventional refresh method in the case of DRAMs therefore has the consequence that even memory cells with longer retention times are refreshed again prematurely. This leads to an unnecessarily high current consumption in the DRAM and shortens, in particular, the operating duration of accumulator- or battery-operated computers having such DRAMs. Since the normal writing and reading operations of the DRAM are interrupted during the refresh operation, e.g. by the presence of a so-called wait command at the processor which controls the DRAM, the availability of the DRAM is also reduced by the short refresh cycles required for the memory cells.
The article OHSAWA, T.; KAI, K.; MURAKAMI, K.: Optimizing the DRAM refresh count for merged DRAM/logic LSIs. IN: International Symposion on Low Power Electronics and Design. Proceedings of the IEEE.ISBN 1-58113-059-7, 1998, pp. 82-87, discloses a generic type of an apparatus for controlling an information refresh operation in memory cells in a memory module and a corresponding generic type of method in which the temporal sequence of the control signals for triggering the refresh operation of individual memory cell rows can be individually adapted to the average retention time of the memory cell row. In this case, it is furthermore possible for the respective refresh cycles to be configured as an integer multiple of a predetermined basic period.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an apparatus for controlling an information refresh operation and a method for controlling an information refresh operation which overcomes the above-mentioned disadvantages of the prior art apparatus and methods of this general type. In particular, it is an object of the invention to provide an apparatus for controlling an information refresh operation and a method for controlling an information refresh operation that enable optimized individual setting of the refresh cycle to the respective retention time of a corresponding memory cell. It is also an object of the present invention, therefore, to develop dynamic random access memories in such a way that the current consumption is reduced and the access time is increased.
With the foregoing and other objects in view there is provided, in accordance with the invention, an apparatus for controlling an information refresh operation in memory cells of a memory module. The apparatus includes: a control device for applying a periodic sequence of control signals to memory cells of a memory module for triggering an information refresh operation in individual ones of the memory cells; and a test circuit for determining a maximum retention time of information in individual ones of the memory cells in the memory module. The test circuit is connected to the control device. The control device is designed to set a temporal sequence of the control signals for triggering the information refresh operation in the individual ones of the memory cells in a variable manner in accordance with the determined maximum retention time of the information in the individual one of the memory cells.
In accordance with an added feature of the invention, the control device is designed to combine the memory cells of the memory module into groups in accordance with the determined maximum retention time of information in the individual ones of the memory cells. The control device assigns, to each individual one of the groups, a respective predetermined time period for applying the control signals to the individual one of the groups. The predetermined time period is an integer multiple of a predetermined basic period.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for controlling an information refresh operation in memory cells in a memory module, that includes steps of: providing a memory module having memory cells; using an upstream test cycle to individually determine a maximum retention time of information in each of the memory cells; applying to the memory cells, a periodic sequence of control signals for triggering an information refresh operation; and setting a temporal sequence of the control signals for triggering the information refresh operation in individual ones of the memory cells in accordance with the determined maximum retention time of the information in the individual ones of the memory cells.
In accordance with an added mode of the invention, the method includes steps of: combining the memory cells in the memory module into groups in accordance with the determined maximum retention time of the information in each of the memory cells; assigning, to each individual one of the groups, a respective predetermined time period for applying the control signals to the individual one of the groups; and providing the predetermined time period as an integer multiple of a predetermined basic period.
In accordance with an additional mode of the invention, the method includes steps of: during the test cycle, for each one of the memory cells: a) reading in a test datum; b) refreshing the test datum with a predetermined frequency; c) reading out the test datum; and d) comparing the test datum that was read in with the test datum that was read out to detect whether or not there is an error. If no error was detected in step d), then steps a) to d) are repeated with a progressively decreased refresh frequency until an error is detected in step d). If the error was detected in step d), then steps a) to d) are repeated with a progressively increased refresh frequency until an error is not detected in step d).
In the case of the invention's control of an information refresh operation in memory cells in a memory module, the temporal sequence of the control signals for triggering the information refresh operation for the individual memory cells is coordinated with the respective maximum retention time of the information in the memory cell.
This design of the refresh driving enables the refresh cycle to be individually adapted to the retention time of the respective cell to be refreshed, that is to say the maximum retention time of the information in the memory cell. Therefore, it is also no longer necessary to define the refresh cycle for the memory module in accordance with the shortest retention time that occurs in the module. The result is that the memory cells with longer retention times are also no longer refreshed unnecessarily prematurely. The reduction of the refresh operations in the memory cells in the memory module, which is possible as a result of the utilization of individual refresh cycles, thus provides for a
Dobler Manfred
Rohleder Markus
Greenberg Laurence A.
Infineon - Technologies AG
Maybeck Gregory L.
Stemer Werner H.
Tran M.
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