Circuit and method for reducing pin count of chip

Details Circuit and method for reducing pin count of chip Circuit and method for reducing pin count of chip

2008-02-04

2009-08-25

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S037000, C326S041000

Reexamination Certificate

active

07579863

ABSTRACT:
A configured setting circuit and method thereof is disclosed. The configured setting circuit includes a multi-phase clock generator, a plurality of terminals, and a decision circuit. The multi-phase clock generator generates a plurality of multi-phase signals with different phases to be outputted via the terminals. The decision circuit detects a phase difference between the input signal and the reference signal and outputs a configuration data according to the phase difference between the input signal and the reference signal.

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patent: 2004/109927 (2004-12-01), None

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