Static information storage and retrieval – Read/write circuit
Reexamination Certificate
2000-02-01
2001-05-15
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
C365S203000, C365S205000, C365S204000
Reexamination Certificate
active
06233179
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to the field of electronic circuits and, in particular, to a circuit and method for reading and writing data in a memory device.
BACKGROUND OF THE INVENTION
Electronic systems typically store data during operation in a memory device. In recent years, the dynamic random access memory (DRAM) has become a popular data storage device for such systems. Basically, a DRAM is an integrated circuit that stores data in binary form (e.g., “1” or “0”) in a large number of cells. The data is stored in a cell as a charge on a capacitor located within the cell. Typically, the cells of a DRAM are arranged in an array so that individual cells can be addressed and accessed. The array can be thought of as rows and columns of cells. Each row includes a word line that interconnects all of the cells on the row with a common control signal. Similarly, each column includes a digit line that is coupled to at most one cell in each row. Thus, the word and digit lines can be controlled so as to individually access each cell of the array.
To read data out of a cell, the capacitor of a cell is accessed by selecting the word line associated with the cell. A complimentary digit line that is paired with the digit line for the selected cell is equilibrated with the voltage on the digit line for the selected cell. When the word line is activated for the selected cell, the capacitor of the selected cell discharges the stored voltage onto the digit line, thus changing the voltage on the digit line. A sense amplifier detects and amplifies the difference in voltage on the pair of digit lines. An input/output device for the array, typically an n-channel transistor, passes the voltage on the digit line for the selected cell to an input/output line for communication to, for example, a processor of a computer or other electronic system associated with the DRAM. In a write operation, data is passed from the input/output lines to the digit lines by the input/output device of the array for storage on the capacitor in the selected cell.
One problem with DRAM design relates to sizing of the input/output devices of the memory array. Typically, the input/output devices are n-channel transistors that are two to eight times smaller than the transistors in the sense amplifier. The ratio of transistor sizes used in a specific design results from trade-offs that relate to the two distinct operations of the input/output device, namely reading and writing data. During a read operation, the input/output device should not affect the voltage on the digit lines. If the input/output devices are too big (e.g., provide too small of a resistance between the sense amplifier and the input/output lines), the input/output devices can trigger the parasitic capacitance of the input/output lines or imbalances in the layout of the sense amplifier such that the data on the digit lines is corrupted. Conversely, during a write operation, the input/output devices need to be able to trigger the sense amplifier to move the voltage on the digit lines to the power supply voltage and ground potential. If the input/output devices of the array are too small, the devices will not provide sufficient current for triggering the sense amplifier when data is to be written to a selected cell over the digit line. Thus, conventional designs require a trade-off with respect to sizing the input/output devices of the memory array.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved circuit and method for reading and writing data in an array of a memory device.
SUMMARY OF THE INVENTION
The above mentioned problems with memory devices and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A memory device is described which uses an input/output device for the array that operates with different drive levels for different access states. For purposes of this specification, one access state is the state of reading data from a memory cell. Another state is the state of writing data to a memory cell.
In particular, an illustrative embodiment of the present invention includes a method for writing and reading data in a memory device. According to this embodiment, the method applies a control signal with a first voltage level to an input/output device of the memory array when reading data from the memory device. The method further applies a control signal with a second voltage level, different from the first voltage level, to the input/output device of the memory array when writing data in the memory device. Specifically, in one embodiment, the voltage level of the control signal is higher during a write operation. By using different voltages on the control signal during different states of an access, the control signal causes the input/output device to provide acceptable drive current during a read operation such that the input/output device does not disturb the data on a pair of digit lines for the cell. Further, the control signal provides sufficient drive current during a write operation to allow the data on input/output lines to be passed to the digit lines.
In another embodiment, the present invention provides a method of writing and reading data in a memory device. According to this embodiment, the method selects a cell of an array of the memory device to be accessed and charges a word line for the selected cell. The method further activates a sense amplifier associated with the charged word line. The method selectively drives an input/output device of the array with different current levels during different states of an access operation. In one embodiment, the method selectively drives an n-channel transistor with different voltage levels during read and write operations.
In another embodiment, the present invention provides a memory device. The memory device includes an array of memory cells that are coupled to a number of word lines and a number of digit lines. The memory device further includes an addressing circuit that is coupled to the array. The addressing circuit selects a memory cell based on a received address signal. An input/output device is coupled to the digit lines of the array. The input/output device includes an input for receiving a control signal. A control circuit is coupled to the input of the input/output device. The control circuit produces a control signal with a first voltage level when reading data from the array and produces a control signal with a second voltage level when writing data to the array.
In another embodiment, the present invention provides a method of accessing a selected cell of a memory device. The method determines the address of the selected cell and activates a sense amplifier that is coupled to control the voltage on a pair of digit lines for the selected cell of the memory device. The method further determines the type of access, e.g., read or write, to be executed for the selected cell of the memory device. Based on the determination, the method generates a variable voltage control signal to activate input/output transistors of the memory array so as to couple data between the digit lines and a pair of complementary input/output lines.
In another embodiment, the present invention provides a memory device. The memory device includes an array of addressable memory cells that are coupled to digit and word lines. An address circuit selects a cell in the array. The memory device also includes a sense amplifier that is coupled to control the voltage on a pair of digit lines for the selected cell of the memory device. The memory device includes input/output transistors that couple the pair of digit lines to a pair of input/output lines. A control circuit of the memory device determines the type of access to be executed for the selected cell of the memory device and generates a variable voltage control signal to
Micro)n Technology, Inc.
Nguyen Viet Q.
Schwegman Lundberg Woessner & Kluth P.A.
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