Static information storage and retrieval – Systems using particular element – Ternary
Reissue Patent
1999-09-30
2003-07-01
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ternary
C365S185030, C365S207000
Reissue Patent
active
RE038166
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a sensing circuit for serial dichotomic sensing of multiple-levels non-volatile memory cells.
BACKGROUND OF THE INVENTION
The market demand for non-volatile memories with higher and higher storage capacity is forcing the semiconductor manufacturers to a continuous effort in scaling the devices and in increasing the chip size.
As an additional possibility to increase the memories' capacities, it has been proposed to store more than one bit per memory cell: a memory device with memory cells capable of storing two or even four bits has a storage capacity two or, respectively, four times higher than that of a memory device with the same chip size but with memory cells capable of storing only one bit each.
Non-volatile memory cells (i.e., memory cells which retain their programming state even in the absence of power) are generally represented by MOS field-effect transistors; data can be programmed in non-volatile memory cells by changing the threshold voltage of the MOS field-effect transistors: in the case of ROMs this is done during their fabrication, while in the case of EPROMs, EEPROMs and Flash EEPROMs, the change in the threshold voltage is achieved by properly biasing the MOS field effect transistors to cause an injection of charges in a floating gate.
To determine the programming state of a non-volatile memory cell, i.e., to “read” or to “sense” the contents of the memory cell, a fixed voltage VG is applied to the control gate of the MOS transistor: the programming state of the memory cell can thus be determined by detecting the position of the threshold voltage of the MOS transistor with respect to said fixed gate voltage.
In the most common case of non-volatile memory cells that are capable of storing only one bit of information, a memory cell can show two different programming states (logic levels), corresponding to two different threshold voltage values; hereinafter, such a cell will be called a “two-level memory cell.” The reading of the memory cells is performed by a so-called “sensing circuit,” which delivers a voltage signal having two distinct possible values, corresponding to the two logic levels.
In the case of non-volatile memory cells that are capable of storing more than one bit of information, a memory cell must be able to show m=2
n
distinct programming states or levels, where n represents the number of bits which can be stored in the memory cell; in the following, such a cell will be called a “multiple-level memory cell.” As in the case of two-level cells, each level corresponds to a different value for the threshold voltage of the MOS transistor.
The discrimination of the m different programming levels can be performed by means of a either a voltage-mode sensing technique or a current-mode sensing technique. In the latter case, for example, the allowed threshold voltage range of the memory cell is divided, on the basis of the electric and physical characteristics of the memory cells, into m sub-intervals, each corresponding to one of the different m levels to be discriminated. The memory cell is then programmed in a desired one of the m different levels by properly adjusting its threshold voltage, so that when the memory cell is biased in the prescribed sensing conditions, it sinks a current corresponding to the desired programming level.
Two sensing techniques have been proposed for multiple-level memory cells: parallel-mode sensing and serial-mode sensing.
Parallel-mode sensing is for example described in A. Bleiker, H. Melchior, “A Four-State EEPROM Using Floating-Gate Memory Cells,” IEEE Journal of Solid State Circuits, vol. SC-22, No. 3, July 1987, pp. 460-463. This technique is the natural extension of the conventional technique used for two-level memory cells, and provides for generating m−1 distinct predetermined references (current references for the current-mode approach, or voltage references for the voltage-mode approach), and for performing m−1 simultaneous comparisons of such m−1 distinct voltage or current references with a current (or a voltage) derived from the memory cell to be read.
The advantages of the parallel-mode sensing technique are its high speed and the independence of the sensing time from the programming state of the memory cell; a disadvantage is the large area required by the sensing circuit, since m−1 distinct comparison circuits are necessary to perform the m−1 simultaneous comparisons.
Differently from parallel-mode sensing serial-mode sensing requires just one reference (current or voltage), which can be varied according to a prescribed law. This single reference is used to perform a series of successive comparisons, and is varied to approximate the analog current or voltage derived from the memory cell to be read. A serial-mode sensing circuit is simple to implement, and requires only a small area.
Two different kinds of serial-mode sensing methodologies are known, which differ in the law according to which the reference is made to vary.
The first methodology, also called “sequential,” described for example in M. Horiguchi et at., “An Experimental Large-Capacity Semiconductor File Memory Using 16-Levels/Cell Storage,” IEEE Journal of Solid State Circuits, vol. SC-23, No. 1, February 1988, pp. 27-32, consists of a succession of comparisons (at most m−1 ) between a fixed quantity (voltage or current) and a variable quantity (voltage or current) which is sequentially varied starting from an initial value.
For example, the fixed quantity can be the current sunk by the memory cell to be read (subject to a prescribed biasing condition), while the variable quantity can be a current supplied by a digitally-driven generator. The (constant) current sunk by the memory cell to be read is compared with a reference current which takes successively increasing (or decreasing) discrete values starting from a minimum (or maximum) value; said discrete values are ideally chosen in such a way as to fall between the different current values corresponding to the m programming levels of the memory cell, so that the result of a comparison is negative (or positive) as long as the reference current is lower (or higher) than the cell's current. The series of successive comparisons stops after the first positive (or negative) result; the last value of the reference current represents the current of the memory cell, except for a constant term associated with the position of the reference current value with respect to the programming levels of the memory cell.
It appears that the time required to read a memory cell with the serial sequential method is not uniform, but depends on the particular programming level of the memory cell and on the starting value of the reference voltage or current (the sensing time depends on the distance between the programming level of the cell to be read and the starting value of the reference voltage or current): from a minimum of one to a maximum of m−1 comparison steps are necessary to determine the programming state of an m-level memory cell. The sensing time soon becomes excessive with an increase in the number of bits stored in a single memory cell.
The second serial-mode sensing methodology, also called “dichotomic,” is described in the co-pending European Patent Application No. 95830023.8 filed on January 27, 1995 in the name of the same applicant. This methodology consists of a successive approximations search that, starting from an initial value for the reference current, finds the value of the memory cell current after a succession of iterations. At each step of the iterative search, the (constant) memory cell current is compared with the variable reference current, whose value is chosen according to a dichotomic or “binary search” algorithm. The initial interval of possible memory cell current values is divided in two parts: depending on the result of the comparison, the successive dichotomy will be applied to only that part of the initial interval wherein the memory cell current falls; the iterative
Calligaro Cristiano
Daniele Vincenzo
Gastaldi Roberto
Manstretta Alessandro
Telecco Nicola
Carlson David V.
Nguyen Tan T.
STMicroelectronics SRL
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