Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent
1998-06-12
2000-07-18
Baker, Stephen M.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
714769, G11B 2018
Patent
active
060922311
ABSTRACT:
A circuit and method use a cyclic redundancy check (CRC) unit to check any errors detected by an error correction code (ECC) unit when reading a sector of bytes from a disk in a disk drive. The CRC unit reads the sector of bytes from the disk simultaneously with the ECC unit. The CRC unit begins generating a residue to detect errors in the sector of bytes at approximately the same time the ECC unit begins generating a residue to detect errors in the sector. The CRC unit does not wait for the ECC unit to finish correcting the sector and transfer the ECC error corrections into a buffer memory before generating a CRC residue. The CRC unit monitors both the sector of bytes read from the disk platter and any errors detected by the ECC unit in the data and CRC bytes, without reading the contents of the buffer unit. The CRC unit uses the error locations and error values found by the ECC unit to determine whether the ECC-corrected bytes stored in a buffer unit were properly corrected. The CRC unit compares any errors detected by the ECC unit with any errors detected by the CRC unit. If the errors detected by the CRC unit do not match the errors detected by the ECC unit, then the CRC unit causes the disk drive to discard the sector of bytes and attempt to reread the same sector from the disk. The CRC error check is completed before any data is transferred to the host computer. The CRC unit must approve of the data before the disk drive controller sends the data to the host. The ECC unit may begin to process another sector of data while the CRC unit is comparing any errors detected by the ECC unit with any errors detected by the CRC unit.
REFERENCES:
patent: 3800281 (1974-03-01), Devore et al.
patent: 4881232 (1989-11-01), Sako et al.
patent: 4949342 (1990-08-01), Shimbo et al.
patent: 5027357 (1992-10-01), Yu et al.
patent: 5068857 (1991-11-01), Yoshida
patent: 5136592 (1992-08-01), Weng
patent: 5157669 (1992-10-01), Yu et al.
patent: 5361266 (1994-11-01), Kodama et al.
patent: 5491701 (1996-02-01), Zook
patent: 5563896 (1996-10-01), Nakagushi
patent: 5581715 (1996-12-01), Verinsky et al.
patent: 5592404 (1997-01-01), Zook
patent: 5600662 (1997-02-01), Zook
patent: 5602857 (1997-02-01), Zook et al.
patent: 5629949 (1997-05-01), Zook
patent: 5691994 (1997-11-01), Acosta et al.
patent: 5991911 (1999-11-01), Zook
Baker Stephen M.
QLogic Corporation
LandOfFree
Circuit and method for rapid checking of error correction codes does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit and method for rapid checking of error correction codes , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for rapid checking of error correction codes will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2049691