Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2006-08-15
2006-08-15
Cao, Chun (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S501000, C713S600000
Reexamination Certificate
active
07093151
ABSTRACT:
An apparatus comprising a circuit configured to (i) generate an output having a frequency and (ii) adjust the frequency in response to a measured duration of a known time interval associated with an input data stream.
REFERENCES:
patent: 4061987 (1977-12-01), Nagahama
patent: 4272760 (1981-06-01), Prazak et al.
patent: 4344067 (1982-08-01), Lee
patent: 4534030 (1985-08-01), Paez et al.
patent: 4689740 (1987-08-01), Moelands et al.
patent: 4692718 (1987-09-01), Roza et al.
patent: 4868525 (1989-09-01), Dias
patent: 4947169 (1990-08-01), Smith et al.
patent: 4993048 (1991-02-01), Williams et al.
patent: 5140197 (1992-08-01), Grider
patent: 5150079 (1992-09-01), Williams et al.
patent: 5175884 (1992-12-01), Suarez
patent: 5200751 (1993-04-01), Smith
patent: 5206857 (1993-04-01), Farleigh
patent: 5304955 (1994-04-01), Atriss et al.
patent: 5319370 (1994-06-01), Signore et al.
patent: 5337335 (1994-08-01), Cloetens et al.
patent: 5345195 (1994-09-01), Cordoba et al.
patent: 5418603 (1995-05-01), Kusumoto et al.
patent: 5428319 (1995-06-01), Marvin et al.
patent: 5440305 (1995-08-01), Signore et al.
patent: 5546433 (1996-08-01), Tran et al.
patent: 5552748 (1996-09-01), O'Shaughnessy
patent: 5559502 (1996-09-01), Schutte
patent: 5563553 (1996-10-01), Jackson
patent: 5565819 (1996-10-01), Cooper
patent: 5583501 (1996-12-01), Henrion et al.
patent: 5594612 (1997-01-01), Henrion
patent: 5604466 (1997-02-01), Dreps et al.
patent: 5666118 (1997-09-01), Gersbach
patent: 5668506 (1997-09-01), Watanabe et al.
patent: 5670915 (1997-09-01), Cooper et al.
patent: 5682049 (1997-10-01), Nguyen
patent: 5686863 (1997-11-01), Whiteside
patent: 5689196 (1997-11-01), Schutte
patent: 5699024 (1997-12-01), Manlove et al.
patent: 5726597 (1998-03-01), Petty et al.
patent: 5796312 (1998-08-01), Hull et al.
patent: 5799177 (1998-08-01), McKenzie et al.
patent: 5818370 (1998-10-01), Sooch et al.
patent: 5825317 (1998-10-01), Anderson et al.
patent: 5870004 (1999-02-01), Lu
patent: 5870345 (1999-02-01), Stecker
patent: 5898345 (1999-04-01), Namura et al.
patent: 5933058 (1999-08-01), Pinto et al.
patent: 6065126 (2000-05-01), Tran et al.
patent: 6157266 (2000-12-01), Tsai et al.
patent: 6158014 (2000-12-01), Henson
patent: 6191660 (2001-02-01), Mar et al.
patent: 6215835 (2001-04-01), Kyles
patent: 6279058 (2001-08-01), Gulick
patent: 6297705 (2001-10-01), Williams et al.
patent: 6407641 (2002-06-01), Williams et al.
patent: 6407682 (2002-06-01), Jones
patent: 6650699 (2003-11-01), Tierno
patent: WO 96/17305 (1996-06-01), None
patent: WO 98/34376 (1998-08-01), None
patent: WO 99/09712 (1999-02-01), None
A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-μm CMOS, By: Beomsup Kim et al., Journal of Solid-State Circuits, vol. 25, No. 6, Dec. 1990, pp. 1385-1394.
WP 3.5: An Integrated Time Reference, By: Robert A. Blauschild, ISSCC94/Session 3, Analog Techniques/Paper WP 3.5, 1994.
Micropower CMOS Temperature Sensor with Digital Output, By: Anton Bakker et al., 1996 IEEE.
CY7C63722/23 CY7C63742/43 enCoRe™ USB Combination Low-Speed USB & PS/2 Peripheral Controller, Cypress Semiconductor Corp., Feb. 2000—Revised Apr. 11, 2000, pp. 1-51.
An Analog PLL-Based Clock and Data Recovery Circuit with High Input Jitter Tolerance, By: Sam Yinshang Sun, Reprinted from IEEE Journal of Solid-State Circuits, vol. SC-24, pp. 325-330, Apr. 1989.
CY7C63221/31 enCoRe™ USB Low Speed USB Peripheral Controller, Cypress Semiconductor Corp., Feb. 2000—Revised Apr. 11, 2000, pp. 1-43.
Timothy J. Williams et al., “Auto-Locking Oscillator for Data Communications”, U.S. Appl. No. 09/511,019, filed Feb. 23, 2000.
Timothy J. Williams et al., “Circuit for Locking an Oscillator to a Data Stream”, U.S. Appl. No. 09/511,020, filed Feb. 23, 2000.
Universal Serial Bus Specification, Revision 2.0, Apr. 27, 2000, pp. 1-622.
Monte F. Mar et al., “Programmable Oscillator Scheme”, U.S. Appl. No. 09/721,316, filed Nov. 22, 2000.
Monte F. Mar et al., “Programmable Oscillator Scheme”, U.S. Appl. No. 09/275,336, filed Mar. 24, 1999.
Cao Chun
Cypress Semiconductor Corp.
Maiorana PC Christopher P.
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