Circuit and method for providing a known logic state at insuffic

Details Circuit and method for providing a known logic state at insuffic Circuit and method for providing a known logic state at insuffic

1995-03-01

1996-08-27

Westin, Edward P.

Electronic digital logic circuitry

Reliability

Fail-safe

326 33, 326121, 326 87, H03K 19007, H03K 1716

Patent

active

055504868

ABSTRACT:
A circuit and method to force an output of a logic circuit to a known state when its supply voltage rises above a predetermined level includes an MOS logic transistor (122) connected between the supply voltage (129) and the output line (130) and connected to receive an input signal (126) on its gate. An MOS state controlling transistor (124) of opposite conductivity type from the MOS logic transistor (122) is connected between the output line (130) and a reference potential (-V.sub.ss), with its gate connected to the gate of the MOS logic transistor (122). A resistor (132) is connected between the supply voltage (128) and the gate of the MOS state controlling transistor (124). If the supply voltage (128) rises above the predetermined level established by the threshold voltage of the MOS state controlling transistor, the MOS state controlling transistor (124) conducts to produce the reference potential on the output line (130). In one embodiment (120), the MOS state controlling transistor (124) is an NMOS transistor and the MOS logic transistor (122) is a PMOS transistor.

REFERENCES:
patent: 4477741 (1984-10-01), Moser, Jr.
patent: 4638187 (1987-01-01), Boler et al.
patent: 4825101 (1989-04-01), Walters, Jr.
patent: 5089722 (1992-02-01), Amedeo
patent: 5149991 (1992-09-01), Rogers
patent: 5206545 (1993-04-01), Huang
patent: 5220209 (1993-06-01), Seymour
patent: 5438280 (1995-08-01), Sugawara

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