Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-06-07
2005-06-07
Lane, Jack A. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S144000, C711S156000, C711S166000, C365S049130, C365S189011, C365S230050
Reexamination Certificate
active
06904502
ABSTRACT:
The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs using a blind invalidate circuit in high-speed memories. In accordance with an embodiment of the present invention, a tag array memory circuit including a plurality of memory bit circuits coupled together to form an n-bit memory cell; and a blind invalidate circuit coupled to a memory bit circuit in the n-bit memory cell, the blind invalidate circuit to clear a bit in the memory bit circuit, if a primary clear bit line is asserted and a received bit value of a right-adjacent memory bit circuit is zero.
REFERENCES:
patent: 4910668 (1990-03-01), Okamoto et al.
patent: 6166939 (2000-12-01), Nataraj et al.
patent: 6510506 (2003-01-01), Nagapudi
patent: 6622284 (2003-09-01), Naffziger et al.
patent: 2002/0087825 (2002-07-01), Nagapudi et al.
Crawford John
Grochowski Edward
Kosaraju Chakravarthy
Mathews Greg S.
Quach Nhon
Kenyon & Kenyon
Lane Jack A.
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