Circuit and method for power clamp triggered dual SCR ESD...

Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Device protection

Reexamination Certificate

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C257S355000, C257S328000, C257S110000, C257S356000, C361S056000, C361S091100, C361S111000

Reexamination Certificate

active

08049250

ABSTRACT:
Circuit and method for RC power clamp triggered dual SCR ESD protection. In an integrated circuit, a protected pad is coupled to an upper SCR circuit and a lower SCR circuit; and both are coupled to the RC power clamp circuit, which is coupled between the positive voltage supply and the ground voltage supply. A structure for ESD protection is disclosed having a first well of a first conductivity type adjacent to a second well of a second conductivity type, the boundary forming a p-n junction, and a pad contact diffusion region in each well electrically coupled to a pad terminal; additional diffusions are provided proximate to and electrically isolated from the pad contact diffusion regions, the diffusion regions and first and second wells form two SCR devices. These SCR devices are triggered, during an ESD event, by current injected into the respective wells by an RC power clamp circuit.

REFERENCES:
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patent: 2003/0076636 (2003-04-01), Ker et al.
patent: 2004/0027744 (2004-02-01), Liu et al.
patent: 2005/0270710 (2005-12-01), Ker et al.
patent: 2007/0018193 (2007-01-01), Ker et al.
patent: 2008/0217650 (2008-09-01), Morishita
patent: 2009/0179222 (2009-07-01), Ker et al.
patent: 2009/0268359 (2009-10-01), Chatty et al.
Ker, M-D., et al., “Native-NMOS-Triggered SCR (NANSCR) for ESD Protection in 0.13-μm CMOS Integrated Circuits,” 42ndAnnual International Reliability Physics Symposium, Phoenix, 2004 IEEE, pp. 381-386.
Mergens, M.P.M, et al., “Diode-Triggered SCR (DTSCR) for RF-ESD Protection of BiCMOS SiGe HBTs and CMOS Ultra-Thin Gate Oxides,” Electronic Devices Meeting, Dec. 8-10, 2003, IEDM '03 Technical Digest, IEEE, pp. 21.3.1-21.3.4.
Morishita, Y., “A PNP-Triggered SCR with Improved Trigger Techniques for High-Speed I/O ESD Protection in Deep Sub-Micron CMOS LSIs,” 27thElectrical Overstress/Electrostatic Discharge Symposium, 2005, pp. 1-7.
Morishita, Y., et al., “A Low-Leakage SCR Design Using Trigger-PMOS Modulations for ESD Protection,” 29thElectrical Overstress/Electrostatic Discharge Symposium 2007, pp. 7A.1-1-7A.1-9.
Ker, M., et al.; “Substrate-Triggered SCR Device for On-Chip ESD Protection in Fully Silicided Sub-0.25-um CMOS Process”, IEEE Trans. Electron. Devices, vol. 50, No. 2, pp. 397-405.

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