Circuit and method for performing tests on memory array cells us

Details Circuit and method for performing tests on memory array cells us Circuit and method for performing tests on memory array cells us

1996-02-27

1997-08-26

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

3651852, 36518907, 36518909, G11C 700, G11C 2900

Patent

active

056616902

ABSTRACT:
An integrated memory circuit (chip) and methods for testing the chip. The chip has an array of memory cells, a sense amplifier for reading selected ones of the cells, and a switch having a first state allowing an external device connected to an external pad to sink a reference current from the sense amplifier and a second state disconnecting the pad from the sense amplifier (so that an internally generated reference current can be supplied to the sense amplifier with the switch in the second state). In the first state, the switch preferably is tolerant of a broad and continuous range of voltages on the pad. In some test modes, cells are read using a sense amplifier of the chip while selected voltages are applied to each cell and external equipment sinks reference current flowing from the sense amplifier through an external pad, thus sensing data from each cell with all the timing constraints usually placed on a read of the cell in the normal mode. In one test mode, all wordlines of the array are disabled and a read cycle is performed to measure all columns of the array sequentially while an external reference current flows between external test equipment and a sense amplifier used for performing the read cycle, and the sense amplifier output indicates whether one or more of the columns has leaky cells.

REFERENCES:
patent: 5444656 (1995-08-01), Bauer et al.
patent: 5539694 (1996-07-01), Rouy

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