Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-04-14
2001-08-14
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S724000, C365S185200, C365S189070, C365S189090, C365S201000
Reexamination Certificate
active
06275961
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention pertains to an integrated memory circuit having memory array cells (e.g., nonvolatile memory cells), which normally reads the cells in a mode in which an internally-generated reference current is provided to (or sunk from) one or more sense amplifiers, but which alternatively operates in a test mode in which an external device sources or sinks a selected external reference current which flows through an external pad to or from the sense amplifiers. The integrated circuit of the invention includes circuitry which operates in a test mode to allow any of a wide range of sense amplifier reference currents to flow through an external pad between at least one sense amplifier and an external device connected to the pad.
2. Description of Related Art
Throughout the specification, including in the claims, the terms “connects” and “connected” are used (in the context that an electronic component is “connected” to another electronic component or “connects” one circuit element to another) in a broad sense to denote that the components are electrically or electromagnetically coupled with sufficient strength under the circumstances. It is not used in a narrow sense requiring that an electrically conducting element is physically connected between the two components.
Nonvolatile memory chips (integrated circuits) with higher density are being introduced to the market each day. In order to achieve higher density, chip manufacturers must continually decrease the size of elements of the chips (such as the size of each cell of a memory array implemented in each chip). With memory array cells having submicron feature sizes, the slightest change in processing of one memory cell relative to another during manufacture results in a big difference in the behavior of the cells with respect to each other.
Many conventional memory chips operate in either a test mode in which input/output (“I/O”) pads are connected directly to an array of memory cells, or in a “normal” (or “active”) mode in which the I/O pads are connected through buffer circuitry to the array of memory cells. In the latter mode (the “normal” mode) the chip can perform read/write operations in which data is written to selected ones of the cells through an input buffer (or data is read from selected ones of the cells through an output buffer).
FIG. 1
is a simplified block diagram of a conventional memory chip of this type. Memory chip
3
of
FIG. 1
includes at least one I/O pad
30
(for asserting output data to an external device or receiving input data from an external device), input/output buffer circuit
10
for I/O pad
30
, test mode switch M
1
, address buffers AO through Ap for receiving memory address bits from an external device, row decoder circuit (X address decoder)
12
, column multiplexer circuit (Y multiplexer)
14
, memory array
16
(comprising columns of nonvolatile memory cells, such as column
16
A), pad
90
, switch
121
connected between pad
90
and other components of chip
3
, and control unit
29
. Each of the cells is preferably a flash memory device, for example of the type described with reference to FIG.
2
. Each of address buffers AO through Ap includes an address bit pad for receiving (from an external device) a different one of address bit signals X
0
through Xn and Y
0
through Ym.
I/O buffer circuit
10
includes a “write” branch and a “read” branch.” The write branch comprises input buffer
18
. The read branch comprises sense amplifier
19
and output buffer
20
.
In the normal operating mode of chip
3
of
FIG. 1
, control unit
29
can cause chip
3
to execute a write operation in which it receives data (to be written to memory array
16
) from an external device at I/O pad
30
, buffers the data in the write branch, and then writes the data to the appropriate memory cell. In this normal operating mode, control unit
29
can also cause chip
3
to execute a read operation in which it amplifies and buffers data (that has been read from array
16
) in the read branch, and then asserts this data to I/O pad
30
.
Although only one I/O pad (pad
30
) is shown in
FIG. 1
, typical implementations of the
FIG. 1
circuit include a plurality of I/O pads, and each I/O pad is buffered by an I/O buffer circuit similar or identical to circuit
10
. For example, one implementation of the
FIG. 1
circuit includes eight I/O pads, eight buffer circuits identical to circuit
10
, one line connected between the output of the output buffer
20
of each buffer circuit and one of the I/O pads (so that eight data bits can be read in parallel from buffers
20
to the pads), and one line connected between the input of the input buffer
18
of each buffer circuit and one of the I/O pads (so that eight data bits can be written in parallel from the pads to buffers
18
). Each I/O pad (including I/O pad
30
) typically has high impedance when the output buffer is not enabled.
Each of the cells (storage locations) of memory array circuit
16
is indexed by a row index (an “X” index determined by decoder circuit
12
) and a column index (a “Y” index output determined by circuit
14
).
FIG. 2
is a simplified schematic diagram of two columns of cells of memory array
16
(with one column, e.g., the column on the right, corresponding to column
16
A of FIG.
1
). The column on the left side of
FIG. 2
comprises “n” memory cells, each cell implemented by one of floating-gate N-channel transistors N
1
, N
3
, . . . , Nn. The drain of each of transistors N
1
-Nn is connected to bitline
13
, and the gate of each is connected to a different wordline (a different one of wordline
0
through wordline n). The column on the right side of
FIG. 2
also comprises “n” memory cells, each cell implemented by one of floating-gate N-channel transistors N
2
, N
4
, . . . , Nm. The drain of each of transistors N
2
-Nm is connected to bitline
15
, and the gate of each is connected to a different wordline (a different one of wordline
0
through wordline n). The source of each of transistors N
1
, N
3
, . . . , Nn, and N
2
, N
4
, . . . , Nm is held at a source potential (which is usually ground potential for the chip during a read or programming operation).
Each memory cell is a nonvolatile memory cell since each of transistors N
1
, N
3
, . . . , Nn, and N
2
, N
4
, . . . , Nm has a floating gate capable of semipermanent charge storage. The current drawn by each cell (i.e., by each of transistors N
1
, N
3
, . . . , Nn, and N
2
, N
4
, . . . , Nm) depends on the amount of charge stored on the cell's floating gate. Thus, the charge stored on each floating gate determines a data value that is stored “semipermanently” in the corresponding cell. In cases in which each of transistors N
1
, N
3
, . . . , Nn, N
2
, N
4
, . . . , and Nm is a flash memory device (as indicated in
FIG. 2
by the symbol employed to denote each of transistors N
1
, N
3
, . . . , Nn, N
2
, N
4
, . . . , and Nm), the charge stored on the floating gate of each is erasable (and thus the data value stored by each cell is erasable) by appropriately changing the voltage applied to the gate and source (in a well known manner).
The manner in which sense amplifier
19
(shown in FIG.
1
and shown directly connected to bitline
13
in
FIG. 2
) is employed to read each cell connected along bitline
13
will next be described.
In response to address bits Y
0
-Ym, Y multiplexer circuit
14
(of
FIG. 1
) determines a column address which selects one of the columns of cells of array
16
(connecting the bitline of the selected column to Node
1
of FIG.
1
), and in response to address bits X
0
-Xn, decoder circuit
12
(of
FIG. 1
) determines a row address which selects one cell in the selected column. Consider an example in which the column address selects the column on the left side of
FIG. 2
(the column including bitline
13
) and the row address selects the cell connected along wordline
0
(the cell comprising transistor N
1
). To read the data value stored in the selected cell, a signal (a curren
Micro)n Technology, Inc.
Moise Emmanuel L.
Schwegman Lundberg Woessner & Kluth P.A.
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