Circuit and method for overflow detection in a digital signal pr

Boots – shoes – and leggings

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G06F 738

Patent

active

059074981

ABSTRACT:
A digital signal processor (DSP) having a serially connected barrel shifter and arithmetic logic unit and overflow detecting method thereof is disclosed. The barrel shifter of the digital signal processor generates a first operand defined as a2.sup.N +A, where -2.sup.M .ltoreq.a<2.sup.M, 0.ltoreq.A<2.sup.N, and M and N are integers, by barrel-shifting an input data operand A. A code extender of the DSP generates a second operand defined as b2.sup.N +B, where b=0 or -1 and 0.ltoreq.B<2.sup.N, by code-extending an input data operand B. An arithmetic logic unit in the DSP adds the first and second operands and generates a result. An overflow detector monitors a parameter a of the first operand, a parameter b of the second operand and an (N-1)-th carry C.sub.N-1 from the arithmetic logic unit in order to detect an overflow condition. An output selector, responsive to an output of the overflow detector, selects either a maximum value of an effective range of the DSP when a positive overflow event occurs, a minimum value of the effective range when a negative overflow event occurs, or the result from the arithmetic logic unit when no overflow event occurs.

REFERENCES:
patent: 4811268 (1989-03-01), Nishitani et al.
patent: 5231600 (1993-07-01), Robidoux et al.
patent: 5260890 (1993-11-01), Suzuki
patent: 5508951 (1996-04-01), Ishikawa
patent: 5745397 (1998-04-01), Nadehara

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