Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2006-11-14
2009-12-15
Lee, Thomas (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C327S149000, C327S161000
Reexamination Certificate
active
07634677
ABSTRACT:
An output circuit includes a detector receiving a parallel data signal, detecting a level change degree for the parallel data signal between a first time point and a second time point, and outputting a select signal according to the level change degree; a delay adjusting device receiving and differentially delaying the parallel data signal into a first and a second delayed parallel data signals with a first and a second delay time, respectively; and a first multiplexer electrically connected to the detector and the delay adjusting device, and selecting one of the first and the second delayed parallel data signals to be outputted in response to the select signal.
REFERENCES:
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patent: 6157229 (2000-12-01), Yoshikawa
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patent: 6998892 (2006-02-01), Nguyen et al.
patent: 2004/0130347 (2004-07-01), Moll et al.
U.S. Appl. No. 10/455,717, titled “Circuit and Method for Outputting Aligned Strobe Signal and Parallel Data Signal,” filed Jun. 5, 2003, with inventor Chi Chang.
Kirton & McConkie
Lee Thomas
Tran Vincent T
Via Technologies Inc.
Witt Evan R.
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