Circuit and method for optimizing memory sense amplifier timing

Details Circuit and method for optimizing memory sense amplifier timing Circuit and method for optimizing memory sense amplifier timing

2008-09-08

2010-06-08

Lam, David (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S230060, C365S194000, C365S205000

Reexamination Certificate

active

07733711

ABSTRACT:
A memory has an array of memory cells, a word line driver, a sense amplifier, and a sense enable circuit. Each memory cell has a coupling transistor for coupling a storage portion to a bit line. The coupling transistors have an average threshold voltage and a maximum threshold voltage. The word line driver is coupled to the array and is for enabling a selected row of memory cells in the array. The sense amplifier detects a state of a memory cell in the selected row in response to a sense enable signal. The sense enable circuit provides the sense enable signal at a time based on the maximum threshold voltage. This timing enables the sense amplifier sufficiently late for low temperature operation while providing for faster operation at high temperature than would normally be achieved using just the average threshold voltage in providing timing of the sense enable signal.

REFERENCES:
patent: 7307896 (2007-12-01), Doyle et al.
Amrutur, Bharadwaj S. et al.; “A Replica Technique for Wordline and Sense Control in Low-Power SRAM's”; IEEE Journal of Solid-State Ciruits; Aug. 1998: pp. 1208-1219; vol. 33, No. 8; IEEE.
Osada, Kenichi et al.; “Universal-Vdd 0.65-2.0-V 32-kB Cache Using a Voltage-Adapted Timing-Generation Scheme and a Lithographically Symmetrical Cell”; IEEE Journal of Solid-State Ciruits; Nov. 2001: pp. 1738-1744; vol. 36, No. 11; IEEE.

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