Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1994-07-14
1998-10-27
An, Meng-Ai T.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395670, 395114, 39575001, 711157, 711218, 382232, 382233, G06F 1200
Patent
active
058288775
ABSTRACT:
A computer system having a central processing unit ("CPU"), a main memory divisible into allocable units, a secondary storage unit and an operating system for allocating the allocable units to tasks for use thereby is provided with a suspend circuit for creating an optimized compressed image of data in the main memory. In a first embodiment, the suspend circuit comprises: (1) a circuit for initiating execution of a reducing task on the CPU, the reducing task requesting the operating system to allocate unallocated ones of the allocable units to the reducing task, (2) a circuit for storing a bit pattern in the allocable units allocated to the reducing task, the bit pattern chosen to optimize performance of a data compression process and (3) a circuit for executing the data compression process to store a compressed image of the main memory in the secondary storage unit, the bit pattern allowing a size of the compressed image to be reduced and a time required to compress and store the compressed image to be minimized. In a second embodiment, the unallocated allocable units are neither compression-optimized, compressed nor stored. Rather, the reducing task creates a record of all allocated units and the data compression process acts on only those allocated units identified in the record.
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Pearce John J.
Zeller Charles
An Meng-Ai T.
Dell USA L.P.
Thlang Eric S.
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