Circuit and method for memory device with defect current isolati

Details Circuit and method for memory device with defect current isolati Circuit and method for memory device with defect current isolati

2000-03-20

2000-11-28

Mai, Son

Static information storage and retrieval

Read/write circuit

Complementing/balancing

365203, 36518909, 365200, G11C 700

Patent

active

061544019

ABSTRACT:
A memory device. The memory device includes an array of word lines and complementary bit line pairs. A number of memory cells are each addressably coupled to intersections of the word line with a bit line of a complementary bit line pair. The memory device also includes addressing circuitry that is coupled to the array so as to select a memory cell. Further, a number of sense amplifiers are provided. Each sense amplifier is coupled to a complementary pair of bit lines. Each complementary pair of bit lines is also coupled to an equilibration circuit. A transistor controllably couples the reference voltage source to the equilibration circuit The transistor is disabled when one of the bit lines of the complementary pair is defective so as to isolate the reference voltage source and prevent leakage current.

REFERENCES:
patent: 5235550 (1993-08-01), Zagar
patent: 5349557 (1994-09-01), Yoshida
patent: 5477496 (1995-12-01), Tanaka et al.
patent: 5673219 (1997-09-01), Hashimoto
patent: 5673231 (1997-09-01), Furutani
patent: 5896334 (1999-04-01), Casper et al.
patent: 5903502 (1999-05-01), Porter
patent: 6002622 (1999-12-01), Dean
patent: 6018481 (2000-01-01), Shiratake
patent: 6041003 (2000-03-01), Casper et al.

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