Circuit and method for memory device with defect current isolati

Details Circuit and method for memory device with defect current isolati Circuit and method for memory device with defect current isolati

1999-02-26

2000-03-21

Mai, Son

Static information storage and retrieval

Read/write circuit

Complementing/balancing

365200, 365203, G11C 700

Patent

active

060410035

ABSTRACT:
A memory device. The memory device includes an array of word lines and complementary bit line pairs. A number of memory cells are each addressably coupled to intersections of the word line with a bit line of a complementary bit line pair. The memory device also includes addressing circuitry that is coupled to the array so as to select a memory cell. Further, a number of sense amplifiers are provided. Each sense amplifier is coupled to a complementary pair of bit lines. Each complementary pair of bit lines is also coupled to an equilibration circuit. A transistor controllably couples the reference voltage source to the equilibration circuit. The transistor is disabled when one of the bit lines of the complementary pair is defective so as to isolate the reference voltage source and prevent leakage current.

REFERENCES:
patent: 5235550 (1993-08-01), Zagar
patent: 5349557 (1994-09-01), Yoshida
patent: 5444662 (1995-08-01), Tanaka et al.
patent: 5477496 (1995-12-01), Tanaka et al.
patent: 5673231 (1997-09-01), Furutani

Affiliated with

Also associated with

Rating

Circuit and method for memory device with defect current isolati does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit and method for memory device with defect current isolati, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for memory device with defect current isolati will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-735569