Circuit and method for measuring delay of high speed signals

Details Circuit and method for measuring delay of high speed signals Circuit and method for measuring delay of high speed signals

2004-11-19

2008-11-18

Nguyen, Vincent Q (Department: 2831)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

Frequency of cyclic current or voltage

C324S076110, C713S501000

Reexamination Certificate

active

07453255

ABSTRACT:
A method and circuit for measuring a time interval between transitions of periodic signals at nodes of a circuit-under-test (CUT), the signals having a periodic clock frequency, the method includes periodically latching a digital value of a first periodic signal at edges of an undersampling clock, simultaneously periodically latching a digital value of a second periodic signal at edges of the undersampling clock, combining the latched digital values of the first and second periodic signals to produce a combined output whose duty cycle is proportional to the time interval between a median edge of latched digital values of the first periodic signal and a median edge of latched digital values of the second periodic signal; and counting the number of undersampling clock cycles in which the combined output is a predetermined logic value within a predetermined time interval whereat the number is proportional to a time interval between a transition of the first periodic signal and a transition of the second periodic signal.

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Huang et al., “An On-chip Short-Time Interval Measurement Technique for testing High-Speed Communication Links”, 2001 VLSI Test Symposium, Apr. 29, 2003 May 2001—Marina Del Rey, CA.
Gillis et. al., “Delay Test of Chip I/Os Using LSSD Boundary Scan”, 1998 International Test Conference, Oct. 18-23, 1998, Washington, D.C. USA.

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