Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1996-08-16
1999-01-12
Lane, Jack A.
Electrical computers and digital processing systems: memory
Address formation
Address mapping
711203, G06F 1202
Patent
active
058601406
ABSTRACT:
Disclosed are a circuit and method for learning attributes of computer memory (such as cacheability and writability) in a computer system. The circuit is coupled to a central processing unit ("CPU") and memory units within the computer system. The circuit is capable of retrieving an attribute relating to performance or operation of a particular memory unit when the CPU accesses the particular memory unit and storing the attribute in random-access memory ("RAM") within the circuit, subsequent accesses by the CPU of the memory unit made more efficient by use of the stored attribute. Operation of the circuit is transparent to the CPU and the memory unit. In an alternative embodiment, the circuit is within the CPU itself.
REFERENCES:
patent: 5091846 (1992-02-01), Sachs et al.
patent: 5353431 (1994-10-01), Doyle et al.
Dell U.S.A. L.P.
Lane Jack A.
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