Circuit and method for latch bypass

Details Circuit and method for latch bypass Circuit and method for latch bypass

2008-04-22

2008-04-22

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C326S104000, C327S407000

Reexamination Certificate

active

11388921

ABSTRACT:
A device includes a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypass value. The device further includes a latch stage having a first input to receive a second data value, a second input to receive the bypass value and an output to provide one of a latched representation of the second data value or a second predetermined value based on the bypass value. The device additionally includes a second combinatorial logic stage having a first input coupled to the output of the first combinatorial logic stage, a second input coupled to the output of the latch stage, and an output.

REFERENCES:
patent: 4314164 (1982-02-01), Tin et al.
patent: 5357146 (1994-10-01), Heimann
patent: 6198700 (2001-03-01), Sassoon
patent: 6525565 (2003-02-01), Young et al.
patent: 6587996 (2003-07-01), Reohr, Jr. et al.
patent: 6697929 (2004-02-01), Cherkauer et al.
patent: 7161390 (2007-01-01), Aipperspach et al.
patent: 2004/0128604 (2004-07-01), Guettaf

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